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參數(shù)資料
| 型號(hào)： | AD8017AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Dual High Output Current, High Speed Amplifier |
| 中文描述： | DUAL OP-AMP, 2600 uV OFFSET-MAX, 100 MHz BAND WIDTH, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 223K |
| 代理商： | AD8017AR |
AD8017
–13–
REV. A
The practical maximum value that these resistors can have is
determined by the offset voltage that is created by the input bias
current that flows through them. The maximum input bias
current into the + inputs is 45
μ
A. This will create an offset
voltage of 45 mV per 1 k
of bias resistor. Fortunately, the ac
coupling of the stages provides only unity gain for this dc offset
voltage, which is another advantage of this configuration. Any
dc offset in the output will limit the amount of dynamic signal
swing that will be available between the rails.
The circuit shown uses two 4.7 V Zener diodes that provide a
voltage drop which serves to limit the power dissipation in the
bias circuit. This allows the use of smaller value resistors in the
bias circuit. Thus, for this circuit the current will be (12 V –
(2
×
4.7 V))/2 k
= 1.3 mA. Thus, this circuit will dissipate
only 15.6 mW, yet only induce a maximum of 40 mV of offset
at the output. This circuit will also track the midpoint of the
supplies over their specified tolerance range.
The distortion of the circuit was measured with a 50
load.
The frequency used was 500 kHz, which is beyond the maxi-
mum required for the upstream signal. For ADSL over POTS, a
maximum frequency of 135 kHz is required. For ADSL over
ISDN, the maximum frequency is 276 kHz. The amplitude was
20 V p-p (10 V p-p for each amplifier), which is the maximum
crest signal that will be required. The second harmonic was
better than –80 dBc, while the third harmonic was –64 dBc.
This represents a worst case of the absolute maximum signal
that will be required for only a very small statistical basis and at
a frequency that is higher than the maximum required. For a
statistical majority of the time, the signal will be at a lower am-
plitude and frequency, where the distortion performance will be
better.
When the circuit was run while providing the upstream drive
signal in an ADSL system, the supply current to the part was
measured at 25 mA. Thus, the total power to the drive circuit
was 300 mW. This power winds up in three places: the drive
amplifier, down the line and in the termination and interface
circuitry.
The ADSL specification calls for 13 dBm or 20 mW into the
line. The line termination will consume an equal amount of
power, as it is the same resistance value. About a 1 dB loss can
be expected in the losses in the interface circuitry, which trans-
lates into about 10 mW of power. Thus, the total power dissi-
pated in the AD8017 when used as a driver in this application is
about 250 mW.
A1
A1
R
L
V
O1
V
O2
VCC
VEE
Figure 40. Differential Driver Simplified Circuit Schematic
It is important to consider the total power dissipation of the
AD8017 in order to properly size the heatsinking area for your
application. The dc power dissipation for V
IN
= 0 is simply,
I
Q
. (V
CC
+ V
EE
), or 2
×
I
Q
×
V
S
. For the AD8017, this number is
0.17 W. In this purely differential circuit we can use symmetry
to simplify the computation for a dc input signal,
P
I
V
V
V
V
R
D
Q
S
S
O
O
L
= ×
2
×
+ ×
(
)
×
4
–
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current commutates during sourcing or
sinking current into the load. For a sine wave source, integra-
tion over a half cycle yields:
P
I
V
V V
R
π
V
R
D
Q
S
S
L
O
L
= ×
2
×
+ ×
2
4
2
(Refer to Figure 41)
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine
wave power overestimates the power dissipation by > 15%. For
example:
P
OUT
= 16
dBm
= 40
mW
V
OUT
@ 50
= 1.41
V rms
or
V
O
= 1.0
V
at each amplifier output, which yields a P
D
of 0.436 W. By
actual measurement, P
D
for a DMT signal of 16 dBm requires
0.38 W of power to be dissipated by the AD8017.
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