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參數資料
| 型號： | AD8033AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Cost, 80 MHz FastFET ⑩ Op Amps |
| 中文描述： | OP-AMP, 3500 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 374K |
| 代理商： | AD8033AR |
REV. B
–16–
AD8033/AD8034
Using the
AD8033/AD8034
, a unity gain peak detector can be
constructed
that will capture a 300 ns pulse while still taking
advantage of the AD8033/AD8034’s low input bias current and
wide common-mode input range, as shown in Figure 5.
Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage
at
Node 3 equal to Node 1. D1 is off and the voltage drop across
R2
is zero. Capacitor C3 speeds up the loop by providing the charge
required by the first amplifier’s input capacitance, helping to
maintain a minimal voltage drop across R2 in the sampling mode.
A negative going edge results in D2 and D3 turning off and D1
turning on, closing the loop around the first amplifier and forcing
V
OUT
– V
IN
across R2. R4 makes the voltage across D2 zero,
minimizing leakage current and kickback from D3 from affecting
the voltage across C2.
The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of V
IN
before the second amplifier’s output can provide negative feedback
at the first amplifier’s summing junction. This is accomplished
with the combination of R1 and C1, which allows the voltage at
Node 1 to settle to 0.1% of V
IN
in 270 ns. The selection of C2
and R3 is made by considering droop rate, settling time, and
kickback. R3 prevents overshoot from occurring at Node 3. The
time constants of R1, C1 and R3, C2 are roughly equal to achieve
the best performance. Slower time constants can be selected by
increasing C2 to minimize droop rate and kickback at the cost
of increased settling time. R1 and C1 should also be increased
to match, reducing the incoming pulse’s effect on kickback.
INPUT
OUTPUT
1.00V/DIV
100nS/DIV
Figure 6. Peak Detector Response 4 V 300 ns Pulse
Figure 6 shows the peak detector in Figure 5 capturing a 300 ns
4 V pulse with 10 mV of kickback and a droop rate of 5 V/s. For
larger peak-peak pulses, the time constants of R1, C1 and R3, C3
should be increased to reduce overshoot. The best droop rate will
occur by isolating parasitic resistances from Node 3. This can be
accomplished using a guard band connected to the output of the
second amplifier that surrounds its summing junction (Node 3).
Increasing both time constants by a factor of 3 permits a
larger
peak pulse to be captured and increases the output accuracy.
AD8034
C3
10pF
R2
1k
R1
1k
AD8034
–V
S
+V
S
C1
39pF/
120pF
LS4148
V
IN
R5
49.9
D1
4.C4
R4
6k
D3
LS4148
–V
S
+V
S
LS4148
R3
200
C2
180pF/560pF
V
OUT
D2
Figure 5. High Speed Unity Gain Peak Detector Using AD8034
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| AD8033AR-EBZ | 功能描述:BOARD EVAL FOR AD8033AR RoHS:是 類別:編程器，開發系統 >> 評估板 - 運算放大器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| AD8033AR-REEL | 制造商:Analog Devices 功能描述:OP Amp Single Volt Fdbk R-R O/P |
| AD8033AR-REEL7 | 制造商:Analog Devices 功能描述:OP Amp Single Volt Fdbk R-R O/P 制造商:Rochester Electronics LLC 功能描述:SOIC, HI-SPD SINGLE FET INPUT AMPLIFIER - Tape and Reel |
| AD8033ARZ | 功能描述:IC OPAMP VF R-R LN LP 60MA 8SOIC RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:FastFET™ 產品培訓模塊:Differential Circuit Design Techniques for Communication Applications 標準包裝:1 系列:- 放大器類型:RF/IF 差分 電路數:1 輸出類型:差分 轉換速率:9800 V/µs 增益帶寬積:- -3db帶寬:2.9GHz 電流 - 輸入偏壓:3µA 電壓 - 輸入偏移:- 電流 - 電源:40mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤，CSP 供應商設備封裝:16-LFCSP-VQ 包裝:剪切帶 (CT) 產品目錄頁面:551 (CN2011-ZH PDF) 其它名稱:ADL5561ACPZ-R7CT |
| AD8033ARZ | 制造商:Analog Devices 功能描述:OP AMP FAST FET SMD 8033 SOIC8 |
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