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參數(shù)資料
| 型號(hào)： | AD8042ACHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | Dual 160 MHz Rail-to-Rail Amplifier |
| 中文描述： | 1 CHANNEL, VIDEO AMPLIFIER, UUC8 |
| 封裝： | DIE |
| 文件頁(yè)數(shù)： | 14/15頁(yè) |
| 文件大小： | 181K |
| 代理商： | AD8042ACHIPS |
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AD8042
REV. A
–14–
HDSL Line Driver
HDSL or high-bit-rate digital subscriber line is becoming popu-
lar as a means to provide data communication at DS1 rates
(1.544 MBPS) over moderate distances via conventional tele-
phone twisted pair wires. In these systems, the transceiver at the
customer’s end is sometimes powered via the twisted pair from a
power source at the central office. It is sometimes required to
raise the dc voltage of the power source to compensate for IR
drops in long lines or lines with narrow gauge wires.
Because of this, it is highly desirable to keep the power con-
sumption of the customer’s transceiver as low as possible. One
means to realize significant power savings is to run the trans-
ceiver from a
±
5 V supply instead of the more conventional
±
12 V.
The high output swing and current drive capability of the
AD8042 make it ideally suited to this application. Figure 41
shows a circuit for the analog portion of an HDSL transceiver
using the AD8042 as the line driver.
2k
V
3k
V
232
V
V
IN
0.001
m
F
V
OUT
6
5
7
1
4
10
5
ATT
2718AF
93DJ39
34
V
2k
V
2k
V
249
V
2k
V
2k
V
2k
V
0.001
m
F
2
3
1
V
REC
1/2
AD8042
2k
V
3k
V
2
3
1
1/2
AD8042
912
V
0.0027
m
F
2
7
9
6
1/4
AD8044
Figure 41. HDSL Line Driver
Layout Considerations
The specified high speed performance of the AD8042 requires
careful attention to board layout and component selection.
Proper RF design techniques and low-pass parasitic component
selection are necessary.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce the stray capacitance.
Chip capacitors should be used for the supply bypassing.
One end should be connected to the ground plane and the
other within 1/8 inch of each power pin. An additional large
(0.47
μ
F–10
μ
F) tantalum electrolytic capacitor should be con-
nected in parallel, but not necessarily so close, to supply current
for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the in-
verting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
or 75
and be properly termi-
nated at each end.
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| AD8042AN | 功能描述:IC OPAMP VF R-R DUAL LP 8DIP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:73 系列:Over-The-Top® 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.07 V/µs 增益帶寬積:200kHz -3db帶寬:- 電流 - 輸入偏壓:1nA 電壓 - 輸入偏移:285µV 電流 - 電源:50µA 電流 - 輸出 / 通道:25mA 電壓 - 電源，單路/雙路(±):2 V ~ 44 V，±1 V ~ 22 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:16-DFN-EP（5x3） 包裝:管件 |
| AD8042AR | 功能描述:IC OPAMP VF R-R DUAL LP 8SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:13 V/µs 增益帶寬積:3MHz -3db帶寬:- 電流 - 輸入偏壓:65pA 電壓 - 輸入偏移:3000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| AD8042AR-EBZ | 功能描述:BOARD EVAL FOR AD8042AR RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 運(yùn)算放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- |
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