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參數資料
| 型號： | AD8045ARD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 3 nV/Hz Ultralow Distortion, High Speed Op Amp |
| 中文描述： | OP-AMP, 1000 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012, SOIC-8 |
| 文件頁數： | 5/24頁 |
| 文件大小： | 474K |
| 代理商： | AD8045ARD |
AD8045
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rev. A | Page 5 of 24
Rating
12.6 V
See Figure 4
V
S
0.7 V to +V
S
+ 0.7 V
±
V
S
V
S
65°C to +125°C
40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, i.e., θ
JA
is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
θ
JA
SOIC
80
LFCSP
93
θ
JC
30
35
Unit
°C/W
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the AD8045 is limited
by the associated rise in junction temperature (T
J
) on the die. At
approximately 150
°
C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric perform-
ance of the AD8045. Exceeding a junction temperature of
175
°
C for an extended period of time can result in changes in
silicon devices, potentially causing degradation or loss of
functionality.
The power dissipated in the package (P
D
) is the sum of the qui-
escent power dissipation and the power dissipated in the die
due to the AD8045 drive at the output. The quiescent power is
the voltage between the supply pins (V
S
) times the quiescent
current (I
S
).
P
D
=
Quiescent Power
+ (
Total Drive Power
–
Load Power
)
(
)
L
2
OUT
R
L
OUT
R
S
S
S
D
V
–
V
2
V
I
V
P
×
+
×
=
RMS output voltages should be considered. If
R
L
is referenced to
V
S
, as in single-supply operation, the total drive power is
V
S
×
I
OUT
. If the rms signal levels are indeterminate, consider the
worst case, when
V
OUT
=
V
S
/4 for
R
L
to midsupply.
(
)
S
S
S
D
R
(
)
L
/
V
I
V
P
2
4
+
×
=
In single-supply operation with
R
L
referenced to
V
S
, worst case
is
V
OUT
=
V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θ
JA
.
Figure 4 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
SOIC (80°C/W) and LFCSP (93°C/W) package on a JEDEC
standard 4-layer board. θ
JA
values are approximations.
0
AMBIENT TEMPERATURE (°C)
120
–40
–20
0
20
40
60
80
100
M
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP
SOIC
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy elec-
trostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
and loss of functionality.
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