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參數資料
| 型號： | AD8048AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 250 MHz, General Purpose Voltage Feedback Op Amps |
| 中文描述： | VIDEO AMPLIFIER, PDIP8 |
| 封裝： | MINI, PLASTIC, DIP-8 |
| 文件頁數： | 14/16頁 |
| 文件大?。?/td> | 478K |
| 代理商： | AD8048AN |
REV. 0
–14–
AD8047/AD8048
H = Absolute Value of Circuit Gain =
Then:
–
R
4
R
1
= 1
k
=
2
π
F
O
C
1
C
2
=
4
C
1(
H
+
1)
α
2
R
1
=
α
2
HK
R
3
=
α
2
K
(
H
+
1)
R
4
=
H
(
R
1)
A/D Converter Driver
As A/D converters move toward higher speeds with higher reso-
lutions, there becomes a need for high performance drivers that
will not degrade the analog signal to the converter. It is desir-
able from a system’s standpoint that the A/D be the element in
the signal chain that ultimately limits overall distortion. This
places new demands on the amplifiers used to drive fast, high
resolution A/Ds.
With high bandwidth, low distortion and fast settling time the
AD8047 and AD8048 make high performance A/D drivers for
advanced converters. Figure 60 is an example of an AD8047
used as an input driver for an AD872, a 12-bit, 10 MSPS A/D
converter.
Layout Considerations
The specified high speed performance of the AD8047 and
AD8048 requires careful attention to board layout and compo-
nent selection. Proper RF design techniques and low pass para-
sitic component selection are mandatory
Figure 60. AD8047 Used as Driver for an AD872, a 12-Bit, 10 MSPS A/D Converter
MSB
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
AV
DD
AGND
V
INA
REF GND
REF IN
REF OUT
AV
SS
AV
SS
AGND
OTR
CLK
DRGND
DRV
DD
DGND
DV
DD
19
18
17
16
15
14
13
12
11
10
9
8
24
25
3
26
28
27
1
20
21
23
22
6
7
4
5
V
INB
0.1
μ
F
–5V ANALOG
AD872
1
6
3
2
5
1
μ
F
+5V ANALOG
AD8047
ANALOG IN
0.1
μ
F
0.1
μ
F
0.1
μ
F
DIGITAL OUTPUT
0.1
μ
F
0.1
μ
F
10
49.9
CLOCK INPUT
0.1
μ
F
0.1
μ
F
+5V ANALOG
+5V DIGITAL
+5V DIGITAL
–5V
ANALOG
2
10
μ
F
10
μ
F
4
7
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance path. The ground plane should be removed from the
area near the input pins to reduce stray capacitance.
Chip capacitors should be used for the supply bypassing (see
Figure 60). One end should be connected to the ground plane
and the other within 1/8 inch of each power pin. An additional
large (0.47
μ
F–10
μ
F) tantalum electrolytic capacitor should be
connected in parallel, though not necessarily so close, to supply
current for fast, large signal changes at the output.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance variations of less than 1 pF at the in-
verting input will significantly affect high speed performance.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). These should be designed with a
characteristic impedance of 50
or 75
and be properly termi-
nated at each end.
Evaluation Board
An evaluation board for both the AD8047 and AD8048 is avail-
able that has been carefully laid out and tested to demonstrate
that the specified high speed performance of the device can be
realized. For ordering information, please refer to the Ordering
Guide.
The layout of the evaluation board can be used as shown or
serve as a guide for a board layout.
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