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參數(shù)資料
| 型號： | AD8057AR-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Cost, High Performance Voltage Feedback, 325 MHz Amplifiers |
| 中文描述： | OP-AMP, 5000 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 184K |
| 代理商： | AD8057AR-REEL7 |
AD8057/AD8058
–12–
REV. A
Video Filter
Some composite video signals that are derived from a digital
source contain some clock feedthrough that can cause problems
with downstream circuitry. This clock feedthrough is usually at
27 MHz, which is a standard clock frequency for both NTSC
and PAL video systems. A filter that passes the video band and
rejects frequencies at 27 MHz can be used to remove these
frequencies from the video signal.
Figure 42 shows a circuit that uses an AD8057 to create a single
+5 V supply, three-pole Sallen-Key filter. This circuit uses a
single RC pole in front of a standard two-pole active section. To
shift the dc operating point to midsupply, ac coupling is pro-
vided by R4, R5 and C4.
2
3
0.1
m
F
+
10
m
F
AD8057
7
4
6
+5V
+5V
R4
10k
V
R5
10k
V
C4
0.1
m
F
R3
49.9
V
R2
499
V
C1
100pF
R1
200
V
R
F
1k
V
C2
680pF
C3
36pF
Figure 42. Low-Pass Filter for Video
Figure 43 shows a frequency sweep of this filter. The response is
down 3 dB at 5.7 MHz, so it passes the video band with little
attenuation. The rejection at 27 MHz is 42 dB, which provides
more than a factor of 100 in suppression of the clock compo-
nents at this frequency.
FREQUENCY – Hz
L
–40
100k
100M
0
1M
10M
–10
–20
–30
–50
–60
–70
–80
–90
10
Figure 43. Video Filter Response
Differential A-to-D Driver
As system supply voltages are dropping, many A-to-D convert-
ers provide differential analog inputs to increase the dynamic
range of the input signal, while still operating on a low supply
voltage. Differential driving can also reduce second and other
even-order distortion products.
Analog Devices offers an assortment of 12- and 14-bit high
speed converters that have differential inputs and can be run
from a single +5 V supply. These include the AD9220, AD9221,
AD9223, AD9224 and AD9225 at 12 bits, and the AD9240,
AD9241, and AD9243 at 14 bits. Although these devices can
operate over a range of common-mode voltages at their analog
inputs, they work best when the common-mode voltage at the
input is at the midsupply or 2.5 V.
Op amp architectures that require upwards of 2V of headroom
at the output have significant problems when trying to drive
such A-to-Ds while operating with a +5 V positive supply. The
low headroom output design of the AD8057 and AD8058 make
them ideal for driving these types of A-to-D converters.
The AD8058 can be used to make a dc-coupled, single-ended-
to-differential driver for one of these A-to-Ds. Figure 44 is a
schematic of such a circuit for driving an AD9225, a 12-bit,
25 MSPS A-to-D converter.
2
3
0.1
m
F
+10
m
F
8
1
+5V
1k
V
1k
V
AD8058
1k
V
1k
V
1k
V
6
1k
V
5
7
1k
V
0.1
m
F
+10
m
F
1k
V
–5V
4
V
IN
0V
50
V
50
V
VINB
VINA
AD9225
+5V
0.1
m
F
+10
m
F
REF
+2.5V
AD8058
Figure 44. Schematic Circuit for Driving AD9225
In this circuit, one of the op amps is configured in the inverting
mode, while the other is in the noninverting mode. However, to
provide better bandwidth matching, each op amp is configured
for a noise gain of 2. The inverting op amp is configured for a
gain of –1, while the noninverting op amp is configured for a
gain of +2. Each of these produces a noise gain of 2, which is
only determined by the inverse of the feedback ratio. The input
signal to the noninverting op amp is divided by 2 in order to
normalize its level and make it equal to the inverting output.
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