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參數資料
| 型號： | AD8057AR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Miniature Enclosed Switches Series 914CE: Ball Bearing Plunger; 1NC 1NO SPDT Snap Action; 12 foot Cable |
| 中文描述： | OP-AMP, 5000 uV OFFSET-MAX, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 13/14頁 |
| 文件大小： | 184K |
| 代理商： | AD8057AR-REEL |
AD8057/AD8058
–13–
REV. A
For zero volts input, the outputs of the op amps want to be at
2.5 V, which is the midsupply level of the A-to-D. This is ac-
complished by first taking the 2.5 V reference output of the
A-to-D and dividing it by two by a pair of 1 k
resistors. The
resulting 1.25 V is applied to each op amp’s positive input. This
voltage is then multiplied by the gain of 2 of the op amps to
provide a 2.5 V level at each output.
The assumption for this circuit is that the input signal is bipolar
with respect to round and the circuit must be dc coupled. This
implies the existence of a negative supply elsewhere in the system.
This circuit uses –5 V as the negative supply for the AD8058.
If the AD8058 negative supply were tied to ground, there would
be a problem at the input of the noninverting op amp. The
input common-mode voltage can only go to within 1V of the
negative rail. Since this circuit requires that the positive inputs
operate with a 1.25 V bias, there is not enough room to swing
this voltage in the negative direction. The inverting stage does
not have this problem, because its common-mode input voltage
remains fixed at 1.25 V. If dc-coupling is not required, various
ac-coupling techniques can be used to eliminate this problem.
Layout
The AD8057 and AD8058 are high speed op amps and should
be used in a board layout that follows standard high speed de-
sign rules. All the signal traces should be as short and direct as
possible. In particular, the parasitic capacitance on the inverting
input of each device should be kept to a minimum to avoid
excessive peaking and other undesirable performance.
The power supplies should be bypassed very close to the power
pins of the package with 0.1
μ
F in parallel with a larger, approxi-
mately 10
μ
F tantalum capacitor. These capacitors should be
connected to a ground plane that is either on an inner layer, or
fills the area of the board that is not used for other signals.
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