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參數資料
| 型號： | AD8129AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Low-Cost 270 MHz Differential Receiver Amplifiers |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數： | 3/28頁 |
| 文件大小： | 510K |
| 代理商： | AD8129AR |
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REV. 0
–3–
AD8129/AD8130
(AD8129 G = 10, AD8130 G = 1, T
A
= 25 C, V
S
= 12 V, REF = 0 V,
PD
≥
V
IH
, R
L
= 1 k , C
L
= 2 pF,
unless otherwise noted. T
MIN
to T
MAX
= –40 C to +85 C, unless otherwise noted.)
12 V SPECIFICATIONS
Model
Parameter
AD8129A
Min
AD8130A
Min
Conditions
Typ
Max
Typ
Max
Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth
V
OUT
≤
0.3 V p-p
V
OUT
= 2 V p-p
V
OUT
≤
0.3 V p-p, SOIC/
μ
SOIC
V
OUT
= 2 V p-p, 25% to 75%
V
OUT
= 2 V p-p, 0.1%
V
OUT
≤
1 V p-p, 10% to 90%
175
170
200
195
50/70
1070
20
1.7
40
250
150
290
175
110
1100
20
1.4
40
MHz
MHz
MHz
V/
μ
s
ns
ns
ns
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Rise and Fall Time
Output Overdrive Recovery
935
960
NOISE/DISTORTION
Second Harmonic/Third Harmonic
V
OUT
= 1 V p-p, 5 MHz
V
OUT
= 2 V p-p, 5 MHz
V
OUT
= 1 V p-p, 10 MHz
V
OUT
= 2 V p-p, 10 MHz
V
OUT
= 2 V p-p, 10 MHz
V
OUT
= 2 V p-p, 10 MHz
f
≥
f
≥
100 kHz
f
≥
100 kHz
AD8130, G = 2, NTSC 200 IRE, R
L
≥
150
AD8130, G = 2, NTSC 200 IRE, R
L
≥
150
–71/–84
–65/–74
–65/–82
–59/–70
–67
25
4.6
1
1.4
0.3
0.1
–79/–86
–74/–81
–74/–80
–74/–74
–70
26
13
1
1.4
0.13
0.2
dBc
dBc
dBc
dBc
dBc
dBm
nV/
√
Hz
pA/
√
Hz
pA/
√
Hz
%
Degrees
IMD
Output IP3
Input Voltage Noise (RTI)
Input Current Noise (+IN, –IN)
Input Current Noise (REF, FB)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Common-Mode Rejection Ratio
DC to 100 kHz, V
=
±
10 V
V
CM
= 1 V p-p @ 2 MHz
V
CM
= 1 V p-p @ 10 MHz
V
CM
= 4 V p-p @ 1 kHz, V
OUT
=
±
0.5 V dc
V
+IN
– V
–IN
= 0 V
92
80
105
88
80
105
dB
dB
dB
dB
V
V
V
M
M
pF
pF
70
93
±
10.3
±
0.5
±
0.75
1
4
3
4
70
80
±
10.5
±
2.5
±
2.8
6
4
3
4
CMRR with V
= 1 V p-p
Common-Mode Voltage Range
Differential Operating Range
Differential Clipping Level
Resistance
±
0.6
±
0.85
±
2.3
±
3.3
Differential
Common-Mode
Differential
Common-Mode
Capacitance
DC PERFORMANCE
Closed-Loop Gain Error
V
OUT
=
±
1 V, R
L
≥
150
T
MIN
to T
V
OUT
=
±
1 V
V
OUT
=
±
1 V
±
0.8
20
87
250
0.2
2
±
1.8
±
0.15
10
73
200
0.4
10
±
0.6
%
ppm/
°
C
dB
ppm
mV
μ
V/
°
C
mV
dB
dB
μ
A
μ
A
nA/
°
C
μ
A
nA/
°
C
Open-Loop Gain
Gain Nonlinearity
Input Offset Voltage
0.8
1.8
T
MIN
to T
MAX
T
MIN
to T
+V
S
= +12 V, –V
S
= –11.0 V to –13.0 V
–V
S
= –12 V, +V
S
= +11.0 V to +13.0 V
1.4
–82
–84
±
2
±
3.5
3.5
–70
–70
±
2
±
3.5
Input Offset Voltage vs. Supply
–88
–92
±
0.25
±
0.5
2.5
±
0.08
0.2
–77
–88
±
0.25
±
0.5
2.5
±
0.08
0.2
Input Bias Current (+IN, –IN)
Input Bias Current (REF, FB)
T
to T
(+IN, –IN, REF, FB)
(+IN, –IN, REF, FB)
T
MIN
to T
MAX
Input Offset Current
±
0.4
±
0.4
OUTPUT PERFORMANCE
Voltage Swing
Output Current
Short Circuit Current
R
LOAD
= 700
±
10.8
±
10.8
V
mA
mA
μ
A/
°
C
pF
40
–60/+55
–240
10
40
–60/+55
–240
10
To Common
T
MIN
to T
PD
≤
V
IL
, In Power-Down Mode
Output Impedance
POWER SUPPLY
Operating Voltage Range
Quiescent Supply Current
Total Supply Voltage
±
2.25
±
12.6
13.9
±
2.25
±
12.6
13.9
V
mA
μ
A/
°
C
mA
mA
13
43
0.73
13
43
0.73
T
MIN
to T
MAX
PD
≤
V
IL
PD
≤
V
IL
,
T
MIN
to T
MAX
0.9
1.1
0.9
1.1
PD
PIN
V
IH
V
IL
I
IH
I
Input Resistance
+V
S
– 1.5
+V
S
– 1.5
V
V
μ
A
μ
A
k
k
μ
s
+V
S
– 2.5
–30
–50
+V
S
– 2.5
–30
–50
PD
= Min V
IH
PD
= Max V
PD
≤
+V
S
– 3 V
PD
≥
+V
S
– 2 V
3
100
0.5
3
100
0.5
Enable Time
Specifications subject to change without notice.
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