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參數資料
| 型號： | AD8130ARM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Low Cost 270 MHz Differential Receiver Amplifiers |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO8 |
| 封裝： | MICRO, SO-8 |
| 文件頁數： | 36/40頁 |
| 文件大小： | 549K |
| 代理商： | AD8130ARM-REEL |
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AD8129/AD8130
Such a connection, also referred to as a cable-tap amplifier, can
be simply made with an AD8130 (see Figure 143). The circuit is
configured with unity gain, and if no output offset is desired,
the REF pin is grounded. The negative differential input is
connected directly to the shield of the cable (or an associated
connector) at the point at which it wants to be tapped.
Rev. C | Page 36 of 40
75
Ω
75
Ω
VIDEO
IN
V
OUT
–V
+V
–V
S
2
PD
+V
S
+
+
AD8130
6
5
4
8
1
3
7
0.1
μ
F
10
μ
F
0.1
μ
F
10
μ
F
0
Figure 143. The AD8130 Can Tap the Video Signal at Any Point Along the
Cable Without Loading the Signal.
The center conductor connects to the positive differential input
of the AD8130. The amplitude of the video signal at this point is
unity, because it is between the two termination resistors. The
AD8130 provides a high impedance to this signal so that the
signal is not disturbed. A buffered unity-gain version of the
video signal appears at the output.
POWER-DOWN
The AD8129/AD8130 have a power-down pin that can be used
to lower the quiescent current when the amplifier is not being
used. A logic low level on the PD pin causes the part to power
down. Because there is no ground pin on the AD8129/AD8130,
there is no logic reference to interface to standard logic levels.
For this reason, the reference level for the PD input is V
S
. If
the AD8129/AD8130 are run with V
S
= 5 V, there is direct
compatibility with logic families. However, if V
S
is higher than
this, a level-shift circuit is needed to interface to conventional
logic levels. A simple level-shifting circuit that is compatible
with common logic families is presented in Figure 144.
AD8129/
AD8130
7
+V
S
+V
S
3 PD
1k
Ω
4.99k
Ω
LOW =
POWER-DOWN
2N2222
OR EQ
0
Figure 144. Circuit that Shifts the Logic Level When V
S
Is Not Equal to
Approximately 5 V.
EXTREME OPERATING CONDITIONS
The AD8129/AD8130 are designed to provide high
performance over a wide range of supply voltages. However,
there are some extremes of operating conditions that have
been observed to produce suboptimal results. One of these
conditions occurs when the AD8130 is operated at unity gain
with low supply voltage—less than approximately ±4 V.
At unity gain, the output drives FB directly. With supplies of
±V
S
less than approximately ±4 V at unity gain, the output can
drive FB’s voltage too close to the rail for the circuit to stay
properly biased. This can lead to a parasitic oscillation.
A way to prevent this is to limit the input signal swing with
clamp diodes. Common silicon-junction signal diodes like the
1N4148 have a forward bias of approximately 0.7 V when about
1 mA of current flows through them. Two series pairs of such
diodes connected antiparallel across the differential inputs can
be used to clamp the input signal and prevent this condition. It
should be noted that the REF input can also shift the output
signal; therefore, this technique only works when REF is at
ground or close to it (see Figure 145).
AD8130
V
OUT
–V
+V
–V
S
PD
+V
S
+
+
V
IN
1N4148
V
IN
6
2
5
4
8
1
3
7
0.1
μ
F
10
μ
F
0.1
μ
F
10
μ
F
0
Figure 145. Clamping Diodes at the Input Limits the Input Swing Amplitude
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| AD8130ARMZ | 功能描述:IC AMP DIFF LN LDIST 40MA 8MSOP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 產品培訓模塊:Differential Circuit Design Techniques for Communication Applications 標準包裝:1 系列:- 放大器類型:RF/IF 差分 電路數:1 輸出類型:差分 轉換速率:9800 V/µs 增益帶寬積:- -3db帶寬:2.9GHz 電流 - 輸入偏壓:3µA 電壓 - 輸入偏移:- 電流 - 電源:40mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤，CSP 供應商設備封裝:16-LFCSP-VQ 包裝:剪切帶 (CT) 產品目錄頁面:551 (CN2011-ZH PDF) 其它名稱:ADL5561ACPZ-R7CT |
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