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參數資料
| 型號： | AD8133ACPZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Triple Differential Driver With Output Pull-Down |
| 中文描述： | TRIPLE LINE DRIVER, QCC24 |
| 封裝： | 4 X 4 MM, LEAD FREE, MO-220VGGD-2, LFCSP-24 |
| 文件頁數： | 5/16頁 |
| 文件大小： | 479K |
| 代理商： | AD8133ACPZ-REEL |
AD8133
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
All V
OCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rev. 0 | Page 5 of 16
Rating
12 V
±V
S
See Figure 3
±V
S
65°C to +125°C
40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, i.e., θ
JA
is specified
for the device soldered in a circuit board in still air.
Table 4. Thermal Resistance with the Underside Pad
Connected to the Plane
Package Type/PCB Type
θ
JA
24-Lead LFCSP/4-Layer
70
Unit
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8133 package is
limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the para-
metric performance of the AD8133. Exceeding a junction tem-
perature of 175°C for an extended period of time can result in
changes in the silicon devices potentially causing failure.
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The load current consists of differential
and common-mode currents flowing to the loads, as well as
currents flowing through the internal differential and common-
mode feedback loops. The internal resistor tap used in the
common-mode feedback loop places a 4 k differential load on
the output. RMS output voltages should be considered when
dealing with ac signals.
Airflow reduces θ
JA
. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground,
and power planes reduces the θ
JA
. The exposed paddle on the
underside of the package must be soldered to a pad on the PCB
surface that is thermally connected to a copper plane in order to
achieve the specified θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package versus ambient temperature for the 24-lead LFCSP
(70°C/W) package on a JEDEC standard 4-layer board with the
underside paddle soldered to a pad that is thermally connected
to a PCB plane. θ
JA
values are approximations.
0
–40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–20
0
20
40
60
80
0
AMBIENT TEMPERATURE (
°
C)
M
LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
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