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參數資料
| 型號： | AD8139ARDZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Noise Rail-to-Rail Differential ADC Driver |
| 中文描述： | OP-AMP, 500 uV OFFSET-MAX, PDSO8 |
| 封裝： | LEAD FREE, MS-012, SOIC-8 |
| 文件頁數： | 18/24頁 |
| 文件大小： | 720K |
| 代理商： | AD8139ARDZ-REEL7 |
AD8139
THEORY OF OPERATION
The AD8139 is a high speed, low noise differential amplifier
fabricated on the Analog Devices second generation eXtra Fast
Complementary Bipolar (XFCB) process. It is designed to
provide two closely balanced differential outputs in response to
either differential or single-ended input signals. Differential
gain is set by external resistors, similar to traditional voltage-
feedback operational amplifiers. The common-mode level of the
output voltage is set by a voltage at the V
OCM
pin and is inde-
pendent of the input common-mode voltage. The AD8139 has
an H-bridge input stage for high slew rate, low noise, and low
distortion operation and rail-to-rail output stages that provide
maximum dynamic output range. This set of features allows for
convenient single-ended-to-differential conversion, a common
need to take advantage of modern high resolution ADCs with
differential inputs.
Rev. A | Page 18 of 24
TYPICAL CONNECTION AND DEFINITION OF
TERMS
Figure 57 shows a typical connection for the AD8139, using
matched external R
F
/R
G
networks. The differential input
terminals of the AD8139, V
AP
and V
AN
, are used as summing
junctions. An external reference voltage applied to the V
OCM
terminal sets the output common-mode voltage. The two
output terminals, V
OP
and V
ON
, move in opposite directions in a
balanced fashion in response to an input signal.
0
+
–
V
AP
V
AN
V
ON
V
OP
–
+
V
O, dm
R
L, dm
AD8139
C
F
R
F
R
G
R
G
C
F
R
F
V
IP
V
OCM
V
IN
Figure 57. Typical Connection
The differential output voltage is defined as
ON
OP
dm
O,
V
V
V
=
(1)
Common-mode voltage is the average of two voltages. The
output common-mode voltage is defined as
2
ON
OP
cm
O,
V
V
V
+
=
(2)
Output Balance
Output balance is a measure of how well V
OP
and V
ON
are
matched in amplitude and how precisely they are 180 degrees
out of phase with each other. It is the internal common-mode
feedback loop that forces the signal component of the output
common-mode towards zero, resulting in the near perfectly
balanced differential outputs of identical amplitude and exactly
180 degrees out of phase. The output balance performance does not
require tightly matched external components, nor does it require
that the feedback factors of each loop be equal to each other. Low
frequency output balance is limited ultimately by the mismatch
of an on-chip voltage divider, which is trimmed for optimum
performance.
Output balance is measured by placing a well matched resistor
divider across the differential voltage outputs and comparing
the signal at the divider’s midpoint with the magnitude of the
differential output. By this definition, output balance is equal to
the magnitude of the change in output common-mode voltage
divided by the magnitude of the change in output differential-
mode voltage:
dm
O,
cm
O,
V
V
Balance
Output
Δ
Δ
=
(3)
The block diagram of the AD8139 in Figure 58 shows the
external differential feedback loop (R
F
/R
G
networks and the
differential input transconductance amplifier, G
DIFF
) and the
internal common-mode feedback loop (voltage divider across
V
OP
and V
ON
and the common-mode input transconductance
amplifier, G
CM
). The differential negative feedback drives the
voltages at the summing junctions V
AN
and V
AP
to be essentially
equal to each other.
AP
AN
V
V
=
(4)
The common-mode feedback loop drives the output common-
mode voltage, sampled at the midpoint of the two 500 resistors,
to equal the voltage set at the V
OCM
terminal. This ensures that
2
dm
O,
OCM
V
OP
V
V
+
=
(5)
and
2
dm
O,
OCM
V
ON
V
V
=
(6)
0
V
OP
V
OCM
G
O
G
DIFF
G
O
G
CM
10pF
10pF
500
500
V
ON
MIDSUPPLY
+
+
V
AN
V
IN
V
IP
V
AP
R
G
R
G
R
F
R
F
Figure 58. Block Diagram
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