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參數(shù)資料
| 型號： | AD8139ARDZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Noise Rail-to-Rail Differential ADC Driver |
| 中文描述： | OP-AMP, 500 uV OFFSET-MAX, PDSO8 |
| 封裝： | LEAD FREE, MS-012, SOIC-8 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 720K |
| 代理商： | AD8139ARDZ-REEL |
AD8139
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
V
OCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rev. A | Page 7 of 24
Rating
12 V
±V
S
See Figure 3
±V
S
–65°C to +125°C
–40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, i.e., θ
JA
is specified
for device soldered in circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
SOIC-8 with EP/4-Layer
LFCSP/4-Layer
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package is
limited by the associated rise in junction temperature (T
J
) on the
die. At approximately 150°C, which is the glass transition tem-
perature, the plastic will change its properties. Even temporarily
exceeding this temperature limit may change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature of
175°C for an extended period of time can result in changes in the
silicon devices potentially causing failure.
θ
JA
70
70
Unit
°C/W
°C/W
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 k
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θ
JA
. Also, more metal directly in contact with
the package leads from metal traces, through holes, ground, and
power planes will reduce the θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package versus the ambient temperature for the exposed paddle
(EP) SOIC-8 (θ
JA
= 70°C/W) package and LFCSP (θ
JA
=
70°C/W) on a JEDEC standard 4-layer board. θ
JA
values are
approximations.
0
–40
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–20
0
20
40
60
80
100
120
0
AMBIENT TEMPERATURE (
°
C)
M
SOIC
AND LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features proprie-
tary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
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