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參數資料
| 型號： | AD8189 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 350 MHz Single-Supply (5 V) Triple 2:1 Multiplexers |
| 中文描述： | 350兆赫單電源（5V）的三重2:1多路復用器 |
| 文件頁數： | 14/24頁 |
| 文件大小： | 725K |
| 代理商： | AD8189 |
AD8188/AD8189
THEORY OF OPERATION
The AD8188 (G = 1) and AD8189 (G = 2) are single-supply,
triple 2:1 multiplexers with TTL-compatible global input
switching and output-enable control. Optimized for selecting
between two RGB (red, green, blue) video sources, the devices
have high peak slew rates, maintaining their bandwidth for
large signals. Additionally, the multiplexers are compensated for
high phase margin, minimizing overshoot for good pixel
resolution. The multiplexers also have respectable video
specifications and are superior for switching NTSC or PAL
composite signals.
The multiplexers are organized as three independent channels,
each with two input transconductance stages and one output
transimpedance stage. The appropriate input transconductance
stages are selected via one logic pin (SEL A/B) such that all
three outputs simultaneously switch input connections. The
unused input stages are disabled with a proprietary clamp
circuit to provide excellent crosstalk isolation between on and
off inputs while protecting the disabled devices from damaging
reverse base-emitter voltage stress. No additional input
buffering is necessary, resulting in low input capacitance and
high input impedance without additional signal degradation.
The transconductance stage is a high slew rate, class AB circuit
that sources signal current into a high impedance node. Each
output stage contains a compensation network and is buffered
to the output by a complementary emitter-follower stage.
Voltage feedback sets the gain with the AD8188 configured as a
unity gain follower, and the AD8189 configured as a gain-of-two
amplifier with a feedback network. This architecture provides
drive for a reverse-terminated video load (150 Ω) with low
differential gain and phase errors, while consuming relatively
little power. Careful chip layout and biasing result in excellent
crosstalk isolation between channels.
HIGH IMPEDANCE DISABLE
The output-enable logic pin (OE) of the AD8188 and AD8189
controls whether the three outputs are enabled or disabled to a
high impedance state. The high impedance disable allows larger
matrices to be built by busing the outputs together.
In the case of the AD8189 (G = 2), the reference buffers also
disable to a state of high output impedance. This feature
prevents the feedback network of a disabled channel from
loading the output, which is valuable when busing together the
outputs of several muxes.
OFF ISOLATION
The off isolation performance of the signal path is dependent
upon the value of the load resistor, R
L
. For calculating off
isolation, the signal path can be modeled as a simple high-pass
network with an effective capacitance of 3 fF. Off isolation
improves as the load resistance is decreased. In the case of the
AD8188, off isolation is specified with a 1 kΩ load. However, a
practical application would likely gang the outputs of multiple
Rev. 0 | Page 14 of 24
muxes. In this case, the proper load resistance for the off
isolation calculation is the output impedance of an enabled
AD8188, typically less than a 1/10 Ω.
FULL POWER BANDWIDTH VS. 3 dB LARGE
SIGNAL BANDWIDTH
Note that full power bandwidth for an undistorted sinusoidal
signal is often calculated using the peak slew rate from the equation
Amplitude
Sinusoid
Rate
Slew
Peak
Bandwidth
Power
Full
×
π
=
2
The peak slew rate is not the same as the average slew rate. The
average slew rate is typically specified as the ratio
t
V
OUT
Δ
Δ
measured between the 20% and 80% output levels of a
sufficiently large output pulse. For a natural response, the peak
slew rate can be 2.7 times larger than the average slew rate.
Therefore, calculating a full power bandwidth with a specified
average slew rate gives a pessimistic result. See the Specifications
section for the large-signal bandwidth and average slew rate for
both the AD8188 and AD8189 (large signal bandwidth is defined
as the 3 dB point measured on a 2 V p-p output sine wave).
Figure 17 and Figure 20 contain plots for the second- and third-
order harmonic distortion. Specifying these three aspects of the
signal path’s large signal dynamics allows the user to predict
system behavior for either pulse or sinusoid waveforms.
SINGLE-SUPPLY CONSIDERATIONS
The AD8188 and AD8189 offer superior large signal dynamics.
The trade-off is that the input and output compliance is limited
to ~1.3 V from either rail when driving a 150 Ω load. The
following sections address some challenges of designing video
systems within a single 5 V supply.
The AD8188
The AD8188 is internally wired as a unity-gain follower. Its
inputs and outputs can both swing to within ~1.3 V of either
rail. This affords the user 2.4 V of dynamic range at input and
output that should be enough for most video signals, whether
the inputs are ac- or dc-coupled. In both cases, the choice of output
termination voltage determines the quiescent load current.
For improved supply rejection, the V
REF
pin should be tied to an
ac ground (the more quiet the supply, the better). Internally, the
V
REF
pin connects to one terminal of an on-chip capacitor. The
capacitor’s other terminal connects to an internal node. The
consequence of building this bypass capacitor on-chip is
twofold. First, the V
REF
pin on the AD8188 draws no input bias
current. (Contrast this to the case of the AD8189, where the
V
REF
pin typically draws 2 μA of input bias current.) Second, on
the AD8188, the V
REF
pin can be tied to any voltage within the
supply range.
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