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參數資料
| 型號： | AD8307AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Cost DC-500 MHz, 92 dB Logarithmic Amplifier |
| 中文描述： | LOG OR ANTILOG AMPLIFIER, 490 MHz BAND WIDTH, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數： | 2/20頁 |
| 文件大小： | 394K |
| 代理商： | AD8307AR |
–2–
REV. A
AD8307–SPECIFICATIONS
(V
S
= +5 V, T
A
= 25
8
C, R
L
≥
1M
V
, unless otherwse noted)
Parameter
Conditions
Min
T yp
Max
Units
GENERAL CHARACT ERIST ICS
Input Range (
±
1 dB Error)
Logarithmic Conformance
Expressed in dBm re 50
f
≤
100 MHz, Central 80 dB
f = 500 MHz, Central 75 dB
Unadjusted
1
–72
16
±
1
dBm
dB
dB
mV/dB
mV/dB
μ
V
dBm
dBm
nV/
√
Hz
dBm
k
pF
ns
±
0.3
±
0.5
25
Logarithmic Slope
vs. T emperature
Logarithmic Intercept
23
23
27
27
Sine Amplitude; Unadjusted
2
Equivalent Sine Power in 50
20
–84
–87
–88
–77
–76
vs. T emperature
Input Noise Spectral Density
Operating Noise Floor
Output Resistance
Internal Load Capacitance
Response T ime
Inputs Shorted
R
SOURCE
= 50
/2
Pin 4 to Ground
1.5
–78
12.5
3.5
400
10
15
Small Signal, 10%-90%,
0 mV–100 mV, C
L
= 2 pF
Large Signal, 10%-90%,
0 V–2.4 V, C
L
= 2 pF
500
ns
Upper Usable Frequency
3
Lower Usable Frequency
500
10
MHz
Hz
Input AC-Coupled
AMPLIFIER CELL CHARACT ERIST ICS
Cell Bandwidth
Cell Gain
–3 dB
900
14.3
MHz
dB
INPUT CHARACT ERIST ICS
DC Common-Mode Voltage
Common-Mode Range
DC Input Offset Voltage
4
Inputs AC-Coupled
Either Input (Small Signal)
R
SOURCE
≤
50
Drift
Differential
Either Pin to Ground
Either Input
3.2
1.6
50
0.8
1.1
1.4
10
V
V
μ
V
μ
V/
°
C
k
pF
μ
A
–0.3
V
S
– 1
500
Incremental Input Resistance
Input Capacitance
Bias Current
25
POWER INT ERFACES
Supply Voltage
Supply Current
Disabled
2.7
5.5
10
750
V
mA
μ
A
V
ENB
≥
2 V
V
ENB
≤
1 V
8
150
NOT ES
1
T his may be adjusted downward by adding a shunt resistor from the Output to Ground. A 50 k
resistor will reduce the nominal slope to 20 mV/dB.
2
T his may be adjusted in either direction by a voltage applied to Pin 5, with a scale factor of 8 dB/V.
3
See Application on 900 MHz operation.
4
Normally nulled automatically by internal offset correction loop. May be manually nulled by a voltage applied between Pin 3 and Ground; see APPLICAT IONS.
Specifications subject to change without notice.
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