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參數資料
| 型號： | AD8316ARM-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Dual Output GSM PA Controller |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO10 |
| 封裝： | MO-187BA, MSOP-10 |
| 文件頁數： | 11/20頁 |
| 文件大小： | 497K |
| 代理商： | AD8316ARM-REEL7 |
REV. C
AD8316
–11–
volts rms; and
V
Z
is the effective intercept voltage, which, as
previously noted, is dependent on waveform but is 199
μ
V rms
for a sine wave input. Now, the current generated by the setpoint
interface is simply
=
/ .15
I
V
k
SET
SET
(4)
I
ERR
, the difference between this current and I
DET
, is applied to
the loop filter capacitor C
FLT
. It follows that the voltage appearing
on this capacitor, V
FLT
, is the time integral of the difference
current
V
I
I
sC
FLT
SET
DET
FLT
( )
(
–
)/
=
(5)
=
V
k
I
V
V
sC
SET
SLP
IN
Z
FLT
/4 15
–
log (
/
)
(6)
The control output V
OUT
is slightly greater than this, since the
gain of the output buffer is
×
1.35. Also, an offset voltage is delib-
erately introduced in this stage, but this is inconsequential, since
the integration function implicitly allows for an arbitrary constant
to be added to the form of Equation 6. The polarity is such that
V
OUT
will rise to its maximum value for any value of V
SET
greater
than the equivalent value of V
IN
. In practice, the output will rail
to the positive supply under this condition unless the control
loop through the power amplifier is present. In other words, the
AD8316 seeks to drive the RF power to its maximum value when-
ever it falls below the setpoint. The use of exact integration results
in a final error that is theoretically zero, and the logarithmic
detection law would ideally result in a constant response time
following a step change of either the setpoint or the power level, if
the power amplifier control function were likewise “linear-in-dB.”
This latter condition is rarely true, however, and
it follows that
the loop response time will, in practice, depend on the power level,
and this effect can strongly influence the design of the control loop.
Equation 6 can be clarified by noting that it can be restated in
the following way
V
V
V
V
V
/
sT
OUT
SET
SLP
IN
Z
(s
–
log (
)
=
(7)
where
V
SLP
is the volts-per-decade slope from Equation 1, having a
value of 440 mV/dec, and
T
is an effective time constant for
the integration, being equal to (4.15 k
×
C
FLT
)/1.35; the resis-
tor value comes from the setpoint interface scaling Equation 4
and the factor 1.35 arises as a result of the voltage gain of the
buffer. So the integration time constant can be written as
T
(
C
in s whenC
is
ressed in nF
exp
FLT
FLT
=
×
)
3 07
.
(8)
To simplify understanding of the control loop dynamics, begin
by assuming that the power amplifier gain function actually is
linear-in-dB; for now, we will also use voltages to express the
signals at the power amplifier input and output. Let the RF output
voltage be V
PA
and its input be V
CW
; further, to characterize the
gain control function, this form is used
V
G V
PA
CW
=
10
(
/
V
)
V
OUT
GSC
(9)
where
G
O
is the gain of the power amplifier when
V
OUT
= 0 and
V
GSC
is the gain scaling. While few amplifiers will conform so
conveniently to this law, it nevertheless provides a clearer starting
point for understanding the more complex situation that arises
when the gain control law is less than ideal.
This idealized control loop is shown in Figure 4. With some
manipulation, it is found that the characteristic equation of this
system is
V
(
s
V
V
V
V
1
kG V
V
/
sT
OUT
SET
GSC
SLP
GSC
+
CW
Z
O
( )
)/
log
(
)
=
10
(10)
where
k
is the voltage coupling factor from the output of the
power amplifier to the input of the AD8316 (e.g.,
×
0.1 for a 20 dB
coupler) and
T
O
is a modified time constant (V
GSC
/V
SLP
)T.
This is quite easy to interpret. First, it shows that a system of
this sort will exhibit a simple single-pole response, for any power
level, with the customary exponential time domain form for
either increasing or decreasing step polarities in the demand
level V
SET
or the carrier input V
CW
. Second, it reveals that the
final value of the control voltage V
OUT
will be determined by
several fixed factors
(
(
)/
V
t
V
V
V
V
kG V
V
/
OUT
SET
GSC
SLP
GSC
CW
Z
= ∞
)
=
log
(
)
10
(11)
RF PA
V
CW
RF DRIVE: UP
TO 2.5GHz
V
RF
DIRECTIONAL COUPLER
C
FLT
AD8316
RESPONSE-SHAPING
OF OVERALL CONTROL
LOOP (EXTERNAL CAP)
V
SET
V
IN
= kV
RF
V
OUT1
Figure 4. Idealized Control Loop for Dynamic
Analysis, OUT1 Selected
Example
Assume that the gain magnitude of the power amplifier runs from
a minimum value of
×
0.316 (–10 dB) at V
OUT
= 0 to
×
100
(40 dB) at V
OUT
= 2.5 V. Applying Equation 9, we find G
O
=
0.316 and V
GSC
= 1 V. Using a coupling factor of k = 0.0316
(that is, a 30 dB directional coupler) and recalling that the nominal
value of V
SLP
is 440 mV and V
Z
= 199
μ
V for the AD8316, we will
first calculate the range of values needed for V
SET
to control an
output range of +32 dBm to –17 dBm. Note that, in the steady
state, the numerator of Equation 7 must be zero, that is
(
log
10
when V
IN
is expanded to
kV
PA
, the fractional voltage sample of
the power amplifier output. Now, for +32 dBm, V
PA
= 8.9 V rms,
this evaluates to
SET
(
0 44
281
1 39
.
V
V
kV
V
SET
SLP
PA
Z
=
)
(12)
V
max
V
mV/
V
)
=
(
)
=
199
10
.
log
(13)
For a delivered power of –17 dBm, V
PA
= 31.6 mV rms,
SET
(
0 44
0 310
.
V
min
V
1. mV/
V
)
=
(
)
=
199
10
.
log
(14)
Note: The power range is 49 dB, which corresponds to a voltage
change of 49 dB
×
22 mV/dB = 1.08 V in
V
SET
.
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