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參數(shù)資料
| 型號(hào)： | AD8391AR-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | xDSL Line Driver 3 V to 12 V with Power-Down |
| 中文描述： | DUAL LINE DRIVER, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 278K |
| 代理商： | AD8391AR-REEL7 |
REV. 0
AD8391
–11–
Power-Down Feature
A three-state power-down function is available via the PWDN pin.
It allows the user to select among three operating conditions: full on,
standby, or shutdown. The
–
V
S
pin is the logic reference for the
PWDN function. The full shutdown state is maintained when the
PWDN is at 0.8 V or less above
–
V
S
. In shutdown the AD8391 will
draw only 4 mA. If the PWDN pin floats, the AD8391 operates in
a standby mode with low impedance outputs and draws approxi-
mately 10 mA.
Power Supply and Decoupling
The AD8391 can be powered with a good quality (i.e., low-noise)
supply anywhere in the range from 3 V to 12 V. The AD8391
can also operate on dual supplies, from
±
1.5 V to
±
6 V. In order
to optimize the ADSL upstream drive capability of +13 dBm and
maintain the best Spurious Free Dynamic Range (SFDR), the
AD8391 circuit should be powered with a well-regulated supply.
Careful attention must be paid to decoupling the power supply.
High-quality capacitors with low equivalent series resistance
(ESR) such as multilayer ceramic capacitors (MLCCs) should
be used to minimize supply voltage ripple and power dissipation.
In addition, 0.1
μ
F MLCC decoupling capacitors should be located
no more than 1
8 inch away from each of the power supply pins.
A large, usually tantalum, 10
μ
F capacitor is required to provide
good decoupling for lower frequency signals and to supply current
for fast, large signal changes at the AD8391 outputs.
Bypassing capacitors should be laid out in such a manner to keep
return currents away from the inputs of the amplifiers. This will
minimize any voltage drops that can develop due to ground cur-
rents flowing through the ground plane. A large ground plane
will also provide a low impedance path for the return currents.
The V
MID
pin should also be decoupled to ground by using a 0.1
μ
F
ceramic capacitor. This will help prevent any high frequency
components from finding their way to the noninverting inputs of
the amplifiers.
Design Considerations
There are some unique considerations that must be taken into
account when designing with the AD8391. The V
MID
pin is internally
biased by two 5 k
resistors forming a voltage divider between
V
CC
and ground. These resistors will contribute approximately
6.3 nV/
√
Hz
of input-referred (RTI) noise. This noise source is
common mode and will not contribute to the output noise when
the AD8391 is used differentially. In a single-supply system,
this is unavoidable. In a dual-supply system,
V
MID
can be connected
directly to ground, eliminating this source of noise.
When V
MID
is left floating, a change in the power supply voltage
(
V) will result in a change of one-half
V at the V
MID
pin. If
the amplifiers
’
inverting inputs are ac-coupled, one-half
V will
appear at the output, resulting in a PSRR of
–
6 dB. If the inputs
are dc-coupled,
V
×
(1 + R
f
/R
g
) will appear at the outputs.
Power Dissipation
It is important to consider the total power dissipation of the
AD8391 to size the heat sink area of an application properly.
Figure 5 is a simple representation of a differential driver. With
some simplifying assumptions the total power dissipated in this
circuit can be estimated. If the output current is large compared to
the quiescent current, computing the dissipation in the output
devices and adding it to the quiescent power dissipation will give
a close approximation of the total power dissipation in the pack-
age. A factor
α
corrects for the slight error due to the Class A/B
operation of the output stage. The value of
α
depends on what
portion of the quiescent current is in the output stage and varies
from 0 to 1. For the AD8391,
α
0.72.
+V
S
–
V
S
+V
O
+V
S
–
V
S
–
V
O
R
L
Figure 5. Simplified Differential Driver
Remembering that each output device only dissipates power for
half the time gives a simple integral that computes the power for
each device:
1
2
2
∫
×
(
–
)
V
V
V
R
S
O
O
L
The total supply power can then be computed as:
P
V
(
V
|
V
R
I V
TOT
S
O
O
L
S
=
∫
∫
)
×
+
4
1
2
2
|
α
In this differential driver, V
O
is the voltage at the output of one
amplifier, so 2 V
O
is the voltage across R
L
. R
L
is the total imped-
ance seen by the differential driver, including any back termination.
Now, with two observations the integrals are easily evaluated.
First, the integral of V
O2
is simply the square of the rms value of
V
O
. Second, the integral of |V
O
| is equal to the average rectified
value of V
O
, sometimes called the mean average deviation, or
MAD. It can be shown that for a DMT signal, the MAD value
is equal to 0.8 times the rms value:
P
V rmsV
V rms
R
I V
TOT
S
L
S
=
×
+
4 0 8
( .
1
2
2
–
)
α
For the AD8391 operating on a single 12 V supply and delivering
a total of 16 dBm (13 dBm to the line and 3 dBm to account for
the matching network) into 50
(100
reflected back through
a 1:2 transformer plus back termination), the dissipated power
is 395 mW.
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