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參數資料
| 型號： | AD8392ARE-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver |
| 中文描述： | QUAD OP-AMP, 5000 uV OFFSET-MAX, PDSO28 |
| 封裝： | MO-153AET, TSSOP-28 |
| 文件頁數： | 12/16頁 |
| 文件大?。?/td> | 529K |
| 代理商： | AD8392ARE-REEL |
AD8392
APPLICATIONS
SUPPLIES, GROUNDING, AND LAYOUT
The AD8392 can be powered from either single or dual supplies,
with the total supply voltage ranging from 10 V to 24 V. For
optimum performance, a well regulated low ripple supply
should be used.
Rev. 0 | Page 12 of 16
As with all high speed amplifiers, close attention should be paid
to supply decoupling, grounding, and overall board layout. Low
frequency supply decoupling should be provided with 10 μF
tantalum capacitors from each supply to ground. In addition, all
supply pins should be decoupled with 0.1 μF quality ceramic
chip capacitors placed as close as possible to the driver. An
internal low impedance ground plane should be used to provide
a common ground point for all driver and decoupling capacitor
ground requirements. Whenever possible, separate ground
planes should be used for analog and digital circuitry.
High speed layout techniques should be followed to minimize
parasitic capacitance around the inverting inputs. Some practi-
cal examples of these techniques are keeping feedback traces as
short as possible and clearing away ground plane in the area of
the inverting inputs. Input and output traces should be kept
short and as far apart from each other as practical to avoid
crosstalk. When used as a differential driver, all differential
signal traces should be kept as symmetrical as possible.
RESISTOR SELECTION
In current feedback amplifiers, selection of feedback and gain
resistors can impact harmonic distortion performance, band-
width, and gain flatness. Care should be exercised in the selec-
tion of these resistors so that optimum performance is achieved.
Table 5 shows some suggested resistor values for use in a variety
of gain settings. These values are suggested as a good starting
point when designing for any application.
Table 5. Resistor Selection Guide
Gain
R
F
1
2.0k
2
1.5k
5
1.0k
10
750
POWER MANAGEMENT
The AD8392 can be configured in any of three active bias states
as well as a shutdown state via the use of two sets of digitally
programmable logic pins. Pins PD(0, 1) 1, 2 control Amplifiers 1
and 2, while PD(0, 1) 3, 4 control Amplifiers 3 and 4. These pins
can be controlled directly with either 3.3 V or 5 V CMOS logic
by using the GND pins as a reference. If left unconnected, the
PD pins float low, placing the amplifier in the full bias mode.
Refer to the Specifications for the per amplifier quiescent cur-
rent for each of the available bias states.
R
G
Open
1.5k
249
82.5
The AD8392 exhibits low output impedance for the three active
states. However, the output impedance in the shutdown state
(PD1, 0 = 1, 1) is undefined.
DRIVING CAPACITIVE LOADS
When driving a capacitive load, most op amps exhibit peaking
in their frequency response. In general, to minimize peaking or
to ensure device stability for larger values of capacitive loads, a
small series resistor can be added between the op amp output
and the load capacitor. Figure 34 shows the frequency response
of the AD8392 for various capacitive loads without any series
resistance. In this condition, the maximum recommended
capacitive load is around 20 pF. As shown in Figure 35, the
addition of a 5.1 series resistor limits peaking to approxi-
mately 3 dB when driving capacitive loads up to 100 pF.
0
G
–15
10
20
0.1
1
10
100
1000
FREQUENCY (MHz)
–10
–5
0
5
15
2k
V
IN
499
50
1k
C
L
10pF
15pF
20pF
Figure 34. AD8392 Capacitive Load Frequency Response
without Series Resistance
0
G
–15
10
20
0.1
1
10
100
1000
FREQUENCY (MHz)
–10
–5
0
5
15
2k
V
IN
499
50
1k
C
L
22pF
47pF
100pF
5.1
Figure 35. AD8392 Capacitive Load Frequency Response
with Series Resistance
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