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參數(shù)資料
| 型號(hào)： | AD8401CHIPS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 8-Bit, 4-Channel Data Acquisition System |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, UUC28 |
| 封裝： | DIE-28 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 225K |
| 代理商： | AD8401CHIPS |
AD8401
–4–
REV. 0
WARNING!
ESD SENSITIVE DEVICE
C AUT ION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8401 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
TIMNGELECTRICAL SPECIFICATIONS
Parameters
1, 2, 3
(@ V
DD
= +5.0 V
6
5%, AG
DAC
= AG
ADC
= 0.0 V; f
CLK
= 5 MHz; –40
8
C
≤
T
A
≤
+85
8
C,
unless otherwse noted)
Symbol
Condition
Min
T yp
Max
Units
DAC T IMING (See Figure 8 T iming Diagram)
WR
Pulse Width
CS
to
WR
Setup T ime
CS
to
WR
Hold T ime
Data Setup T ime
Data Hold T ime
t
1
t
2
t
3
t
4
t
5
50
0
0
60
0
ns
ns
ns
ns
ns
ADC T IMING (See Figures 6 and 7 T iming Diagrams)
ST
Pulse Width
ST
to
BUSY
Delay
BUSY
to
INT
Delay
BUSY
to
CS
Delay
CS
to
RD
Setup T ime
RD
Pulse Width
4
CS
to
RD
Hold T ime
Data Access after
RD
Data Access after
RD
Bus Relinquish after
RD
RD
to
INT
Delay
RD
to
BUSY
Delay
Data Valid after
BUSY
Data Valid after
BUSY
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
13
t
14
t
15
t
16
t
17
t
17
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
110
30
0
0
75
0
10
10
10
C
L
= 20 pF
C
L
= 100 pF
75
135
70
85
110
90
135
C
L
= 20 pF
C
L
= 100 pF
NOT ES
1
All input control signals are specified with t
= t
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t
13
and t
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3
t
14
is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
4
t
15
is determined by t
13
.
+5V
ABSOLUT E MAX IMUM RAT INGS*
Supply Voltage (V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V
Input Voltages . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Package Power Dissipation . . . . . . . . . . . . . . (T
J
max–T
A
)/
θ
JA
T hermal Resistance
θ
JA
28-Lead SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . 53
°
C/W
Storage T emperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Operating T emperature Range . . . . . . . . . . . . –40
°
C to +85
°
C
Junction T emperature Range (T
J
max) . . . . –65
°
C to +150
°
C
Lead T emperature Range (Soldering, 60 sec) . . . . . . +300
°
C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDE RING GUIDE
T emperature
Range
Package
Description
Package
Option
Model*
AD8401AR
AD8401Chips
–40
°
C to +85
°
C
+25
°
C
28-Lead SOIC
Die
SOL-28
*T he AD8401 contains 1257 transistors.
Figure 1. Load Circuits for Data Access Time Test
a. V
OH
to High Z
a. High Z to V
OH
b. High Z to V
OL
DGND
CL
3k
DBN
DBN
CL
3k
DGND
DGND
10pF
3k
DBN
DBN
10pF
3k
+5V
DGND
b. V
OL
to High Z
Figure 2. Load Circuits for Bus Relinquish Time Test
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