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參數資料
| 型號： | AD8403AN50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字電位計 |
| 英文描述： | 32-Tap. Nonvolatile. Linear-Taper Digital Potentiometers in SOT23 |
| 中文描述： | QUAD 50K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDIP24 |
| 封裝： | PLASTIC, MS-001, DIP-24 |
| 文件頁數： | 13/20頁 |
| 文件大小： | 496K |
| 代理商： | AD8403AN50 |
AD8400/AD8402/AD8403
REV. B
–13–
where Dx is the data contained in the 8-bit RDAC# latch, and
R
BA
is the nominal end-to-end resistance. For example, when
V
A
= 0 V and B terminal is open circuit, the following output
resistance values will be set for the following RDAC latch codes
(applies to 10 k
potentiometers):
D
(Dec)
R
WA
(
)
Output State
255
128
1
0
89
5050
10011
10050
Full Scale
Midscale (
RS
= 0 Condition)
1 LSB
Zero Scale
The typical distribution of R
BA
from channel-to-channel matches
within
±
1%. However, device-to-device matching is process lot
dependent having a
±
20% variation. The change in R
BA
with
temperature has a positive 500 ppm/
°
C temperature coefficient.
The wiper-to-end-terminal resistance temperature coefficient
has the best performance over the 10% to 100% of adjustment
range where the internal wiper contact switches do not contribute
any significant temperature related errors. The graph in Figure
11 shows the performance of R
WB
tempco vs. code, using the
trimmer with codes below 32 results in the larger temperature
coefficients plotted.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example, connecting A terminal to +5 V and B terminal to
ground produces an output voltage at the wiper starting at zero
volts up to 1 LSB less than +5 V. Each LSB of voltage is equal
to the voltage applied across terminal AB divided by the 256
position resolution of the potentiometer divider. The general
equation defining the output voltage with respect to ground for
any given input voltage applied to terminals AB is:
V
W
(
Dx
) =
Dx
/256
×
V
AB
+
V
B
Operation of the digital potentiometer in the divider mode re-
sults in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value; therefore, the temperature drift improves
to 15 ppm/
°
C.
At the lower wiper position settings, the potentiometer divider
temperature coefficient increases due to the contributions of the
CMOS switch wiper resistance becoming an appreciable portion
of the total resistance from terminal B to the wiper. See Figure 10
for a plot of potentiometer tempco performance versus code
setting.
Equation 4
DIGITAL INTERFACING
The AD8400/AD8402/AD8403 contains a standard SPI com-
patible three-wire serial input control interface. The three inputs
are clock (CLK),
CS
and serial data input (SDI). The positive-
edge sensitive CLK input requires clean transitions to avoid
clocking incorrect data into the serial input register. For best re-
sults use logic transitions faster than 1 V/
μ
s. Standard logic
families work well. If mechanical switches are used for product
evaluation, they should be debounced by a flip-flop or other
suitable means. The Figure 38 block diagrams show more detail
of the internal digital circuitry. When
CS
is taken active low, the
clock loads data into the 10-bit serial register on each positive
clock edge (see Table II).
R
DAC
LAT
#1
GND
A1
W1
B1
V
DD
AD8400
CS
CLK
8
D7
D0
EN
DEC
A1
A0
SDI
DI
REG
D0
D7
SER
a.
R
DAC
LAT
#1
R
AGND
RS
A1
W1
B1
V
DD
AD8402
CS
CLK
8
D7
D0
R
DAC
LAT
#2
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
SDI
DI
1SER
REG
D0
SHDN
DGND
D7
b.
R
DAC
LAT
#1
R
AGND
RS
A1
W1
B1
V
DD
AD8403
CS
CLK
SDO
8
D7
D0
R
DAC
LAT
#4
R
A4
W4
B4
D7
D0
EN
ADDR
DEC
A1
A0
D7
SDI
DO
DI
SER
REG
D0
SHDN
DGND
c.
Figure 38. Block Diagrams
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