
AD8591/AD8592/AD8594
–11–
REV. A
The U1-A amplifier is configured as a unity gain buffer driving a
1 nF capacitor. The input signal is connected to the noninverting
input, while the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows V
IN
. Once the sample clock goes
low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.
The U1-B amplifier is used as a unity gain buffer to prevent load-
ing on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is very little voltage droop from C1
during the Hold period. This circuit can be used with sample
frequencies as high as 500kHz and as low as below 1Hz. Even
lower voltage droop can be achieved for very low sample rates
by increasing the value of C1.
Direct Access Arrangement for PCMCIA Modems
(Telephone Line Interface)
Figure 38 illustrates a +5V transmit/receive telephone line
interface for 600
systems. It allows full duplex transmission of
signals on a transformer-coupled 600
line in a differential
manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the AD8594’s high output
current drive and low dropout voltages, the largest signal avail-
able on a single +5V supply is approximately 4.5Vp-p into a
600
transmission system. Amplifier A3 is configured as a
difference amplifier for two reasons: (1)It prevents the transmit
signal from interfering with the receive signal and (2)it extracts
the receive signal from the transmission line for amplification by
A4. Amplifier A4’s gain can be adjusted in the same manner as
A1’s to meet the modem’s input signal requirements. Standard
resistor values permit the use of SIP (Single In-line Package)
format resistor arrays. Couple this with the AD8594 16-lead
TSSOP or SOIC footprint, and this circuit offers a compact,
cost effective solution.
R7
10k
V
R8
10k
V
+5V
6.2V
6.2V
TRANSMIT
TxA
RECEIVE
RxA
C1
0.1
m
F
R1
10k
V
R2
9.09k
V
2k
V
P1
Tx GAIN
ADJUST
A1
A2
A3
A4
A1, A2 = 1/2 AD8592
A3, A4 = 1/2 AD8592
R3
360
V
1:1
T1
TO TELEPHONE
LINE
1
2
3
9
8
7
2
3
1
8
7
9
10
m
F
R5
10k
V
R6
10k
V
R9
10k
V
R14
14.3k
V
R10
10k
V
R11
10k
V
R12
10k
V
R13
10k
V
C2
0.1
m
F
P2
Rx GAIN
ADJUST
2k
V
Z
O
600
V
MIDCOM
671-8005
SHUTDOWN
6
5
6
5
Figure 38. A Single Supply Direct Access Arrangement for
PCMCIA Modems
Single Supply Differential Line Driver
Figure 39 shows a single supply differential line driver circuit that
can drive a 600
load with less than 0.7% distortion from 20 Hz
to 15 kHz with an input signal of 4 V p-p and a single +5 V supply.
The design uses an AD8594 to mimic the performance of a fully
balanced transformer based solution. However, this design occu-
pies much less board space while maintaining low distortion and
can operate down to dc. Like the transformer based design, either
output can be shorted to ground for unbalanced line driver applica-
tions without changing the circuit gain of 1.
R3
10k
V
R
L
600
V
C1
22
m
F
A2
9
8
7
3
1
2
A1
+5V
R1
10k
V
R2
10k
V
R11
10k
V
R7
10k
V
8
7
7
A1
+5V
+5V
R8
100k
V
R9
100k
V
C2
1
m
F
R12
10k
V
R14
50
V
A2
1
2
3
R6
10k
V
R13
10k
V
C3
47
m
F
V
O1
V
O2
C4
47
m
F
A1, A2 = 1/2 AD8592
GAIN =R2
SET: R7, R10, R11 = R2
SET: R6, R12, R13 = R3
V
IN
R10
10k
V
R5
50
V
10
4
10
4
9
Figure 39. A Low Noise, Single Supply Differential
Line Driver
R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the input’s dc voltage is equal to half of
the supply voltage.
The circuit can also be configured to provide additional gain if
desired. The gain of the circuit is:
A
V
V
R
R
V
OUT
IN
=
=
3
2
(7)
Where:
V
OUT
= V
O1
–V
O2
,
R2
= R7 = R10 = R11 and,
R3
= R6 = R12 = R13