參數資料
| 型號： | AD8600APZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC MULT 16CH 8BIT 44PLCC |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 500 |
| 設置時間： | 1µs |
| 位數： | 8 |
| 數據接口： | 并聯 |
| 轉換器數目： | 16 |
| 電壓電源： | 模擬和數字，雙 ± |
| 功率耗散（最大）： | 175mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應商設備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 16 電壓，單極；16 電壓，雙極 |
| 采樣率（每秒）： | 1M |
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FUNCTIONAL BLOCK DIAGRAM
R/W
V
DD1
LD
CONTROL
LOGIC
ADDRESS
DECODE
16 x 8
INPUT
REGISTERS
RS
V
DD2
V
REF
V
CC
16 x 8
DAC
REGISTERS
16
8-BIT
DACS
CS
EN
A3
A2
A1
A0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
V
EE
D
GND1
D
GND2
DACGND
AD8600
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
16-Channel, 8-Bit
Multiplying DAC
AD8600
FEATURES
16 Independently Addressable Voltage Outputs
Full-Scale Set by External Reference
2
s Settling Time
Double Buffered 8-Bit Parallel Input
High Speed Data Load Rate
Data Readback
Operates from Single +5 V
Optional
±6 V Supply Extends Output Range
APPLICATIONS
Phased Array Ultrasound & Sonar
Power Level Setting
Receiver Gain Setting
Automatic Test Equipment
LCD Clock Level Setting
GENERAL DESCRIPTION
The AD8600 contains 16 independent voltage output digital-to-
analog converters that share a common external reference input
voltage. Each DAC has its own DAC register and input register
to allow double buffering. An 8-bit parallel data input, four ad-
dress pins, a CS select, a LD, EN, R/W, and RS provide the
digital interface.
The AD8600 is constructed in a monolithic CBCMOS process
which optimizes use of CMOS for logic and bipolar for speed
and precision. The digital-to-analog converter design uses volt-
age mode operation ideally suited to single supply operation.
The internal DAC voltage range is fixed at DACGND to VREF.
The voltage buffers provide an output voltage range that ap-
proaches ground and extends to 1.0 V below VCC. Changes in
reference voltage values and digital inputs will settle within
±1 LSB in 2 s.
Data is preloaded into the input registers one at a time after the
internal address decoder selects the input register. In the write
mode (R/W low) data is latched into the input register during
the positive edge of the EN pulse. Pulses as short as 40 ns can
be used to load the data. After changes have been submitted to
the input registers, the DAC registers are simultaneously up-
dated by a common load EN
× LD strobe. The new analog out-
put voltages simultaneously appear on all 16 outputs.
At system power up or during fault recovery the reset (RS) pin
forces all DAC registers into the zero state which places zero
volts at all DAC outputs.
The AD8600 is offered in the PLCC-44 package. The device is
designed and tested for operation over the extended industrial
temperature range of –40
°C to +85°C.
VDD1
DACGND
R/WCSADDRESS
RS
VDD2
VREF
VCC
DGND2
DGND1
R-2R
DAC
LDEN
VEE
RS
R/WCSADDREN
OX
DAC
REGISTER
INPUT
REGISTER
DB7...DB0
Figure 1. Equivalent DAC Channel
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