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參數資料
| 型號： | AD871JD |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 5 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-28 |
| 文件頁數： | 14/16頁 |
| 文件大小： | 378K |
| 代理商： | AD871JD |
AD871
REV. A
–14–
82 mA, while the typical current out of AV
SS
is 115 mA. Typi-
cally, 33 mA will flow into the AGND pin.
Careful design and the use of differential circuitry provide the
AD871 with excellent rejection of power supply noise over a
wide range of frequencies, as illustrated in Figure 29.
–75
–100
–85
–95
100k
–90
10k
–80
10M
1M
FREQUENCY – Hz
S
DV
DD
AV
DD
AV
SS
Figure 29. Power Supply Rejection vs. Frequency,
100 mV p-p Signal on Power Supplies
Figure 30 shows the degradation in SNR resulting from 100 mV
of power supply ripple at various frequencies. As Figure 30
shows, careful decoupling is required to realize the specified dy-
namic performance. Figure 34 demonstrates the recommended
decoupling strategy for the supply pins. Note that in extremely
noisy environments, a more elaborate supply filtering scheme
may be necessary.
FREQUENCY – Hz
10k
100k
10M
1M
S
72
66
60
64
62
68
70
AV
DD
DV
DD
AV
SS
Figure 30. SNR vs. Supply Noise Frequency (f
IN
= 1 MHz)
DIGITAL SUPPLIES AND GROUNDS
The digital activity on the AD871 chip falls into two general cat-
egories: CMOS correction logic, and CMOS output drivers.
The internal correction logic draws relatively small surges of
current, mainly during the clock transitions; in the 44-terminal
package, these currents flow through pins DGND and DV
DD
.
The output drivers draw large current impulses while the output
bits are changing. The size and duration of these currents is a
function of the load on the output bits: large capacitive loads are
to be avoided. In the 44-terminal package, the output drivers are
supplied through dedicated pins DRGND and DRV
DD
. Pin
count constraints in the 28-lead packages require that the digital
and driver supplies share package pins (although they have sepa-
rate bond wires and on-chip routing). The decoupling shown in
Figure 34 is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionately, and/or using external
buffers/latches.
APPLICATIONS
OPTIONAL ZERO AND GAIN TRIM
The AD871 is factory trimmed to minimize zero error, gain
error and linearity errors. In some applications the zero and gain
errors of the AD871 need to be externally adjusted to zero. If
required, both zero error and gain error can be trimmed with
external potentiometers as shown in Figure 31. Note that gain
error adjustments must be made with an external reference.
Zero trim should be adjusted first. Connect V
INA
to ground and
adjust the 10 k
potentiometer so that a nominal digital output
code of 0000 0000 0000 (twos complement output) exists. Note
that the zero trim should be decoupled and that the accuracy of
the
±
2.5 V reference signals will directly affect the offset.
Gain error may then be calibrated by adjusting the REF IN volt-
age. The REF IN voltage should be adjusted such that a +1 V
input on V
INA
results in the digital output code 01111 1111
1111 (twos complement output).
+2.5V
–2.5V
V
INB
AD871
0.1
m
F
10
m
F
10k
V
(a) ZERO TRIM
Figure 31. Zero and Gain Error Trims
REF IN
AD871
TRIM
V
OUT
AD
REF43
(b) GAIN TRIM
100k
V
DIGITAL OFFSET CORRECTION
The AD871 provides differential inputs that may be used to cor-
rect for any offset voltages on the analog input. For applications
where the input signal contains a dc offset, it may be advanta-
geous to apply a nulling voltage to the V
INB
input. Applying a
voltage equal to the dc offset will maximize the full-scale input
range and therefore the dynamic range. Offsets ranging from
–0.7 V to +0.5 V can be corrected.
Figure 32 shows how a dc offset can be applied using the AD568
12-bit, high speed digital-to-analog converter (DAC). This cir-
cuit can be used for applications requiring offset adjustments on
every clock cycle. The AD568 connection scheme is used to
provide a –0.512 V to +0.512 V output range. The offset voltage
must be stable on the rising edge of the AD871 clock input.
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