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參數資料
| 型號： | AD9215BCP-65EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| 中文描述： | 10位，65/80/105 MSPS的，3V的A / D轉換 |
| 文件頁數： | 14/36頁 |
| 文件大小： | 1416K |
| 代理商： | AD9215BCP-65EB |
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AD9215
APPLYING THE AD9215 THEORY OF OPERATION
The AD9215 architecture consists of a front-end SHA followed
by a pipelined switched capacitor ADC. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 10-bit result in the digital correction logic. The pipe-
lined architecture permits the first stage to operate on a new
input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Rev. A | Page 14 of 36
The input stage contains a differential SHA that can be config-
ured as ac-coupled or dc-coupled in differential or single-ended
modes. Each stage of the pipeline, excluding the last, consists of
a low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipe-
line. Redundancy is used in each one of the stages to facilitate
digital correction of flash errors.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjust-
ment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
Analog Input and Reference Overview
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum perform-
ance while processing a differential input signal. The SHA input
can support a wide common-mode range and maintain excel-
lent performance, as shown in Figure 31. An input common-
mode voltage of midsupply minimizes signal-dependent errors
and provides optimum performance.
0
H
H
VIN+
VIN–
C
PAR
C
PAR
T
T
0.5pF
0.5pF
T
T
Figure 30. Switched-Capacitor SHA Input
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 30). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s in-
put; therefore, the precise values are dependent upon the appli-
cation. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they would limit the input bandwidth.
The analog inputs of the AD9215 are not internally dc biased.
In ac-coupled applications, the user must provide this bias ex-
ternally.
V
CM
=
AVDD
/2 is recommended for optimum per-
formance, but the device functions over a wider range with rea-
sonable performance (see Figure 31).
0
40
0.25
45
50
55
60
65
70
75
80
85
0.75
1.25
1.75
2.25
2.75
d
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2V p-p SFDR
2V p-p SNR
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
For best dynamic performance, the source impedances driving
VIN+ and VIN should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as
REFT
= 1/2
(
AVDD
+
VREF
)
REFB
= 1/2 (
AVDD
VREF
)
Span
=
2
×
(
REFT
REFB
)
=
2 ×
VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed val-
ues of 0.5 V or 1.0 V or adjusted within the same range as dis-
cussed in the Internal Reference Connection section. Maximum
相關PDF資料 |
PDF描述 |
|---|---|
| AD9215 | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BCP-80 | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BCP-80EB | 10-Bit, 65/80/105 MSPS, 3V A/D Converter |
| AD9215BCPZ-65 | Circular Connector; No. of Contacts:15; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 |
| AD9215BRU-105 | Circular Connector; No. of Contacts:15; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-15 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9215BCP-65EBZ | 功能描述:BOARD EVAL FOR AD9215BCP-65 RoHS:是 類別:編程器，開發系統 >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率（每秒）:94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9215BCP-80 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 80Msps 10-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT LOW POWER 65/80/105 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:10BIT ADC 80MSPS 9215 LFCSP-32 |
| AD9215BCP-80EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9215 3 V A/D Converter ,10-Bit, 65/80/105 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR AD9215 3V A/D CNVRTR ,10-BIT, 65/80/105 MSPS - Bulk |
| AD9215BCP-80EBZ | 功能描述:BOARD EVAL FOR AD9215BCP-80 RoHS:是 類別:編程器，開發系統 >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率（每秒）:94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9215BCPZ-105 | 功能描述:IC ADC 10BIT 105MSPS 3V 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1,000 系列:- 位數:12 采樣率（每秒）:300k 數據接口:并聯 轉換器數目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數目和類型:1 個單端，單極；1 個單端，雙極 |
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