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參數資料
| 型號： | AD9216BCPZRL7-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| 中文描述： | 2-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-220-VMMD, LFCSP-64 |
| 文件頁數： | 13/20頁 |
| 文件大?。?/td> | 298K |
| 代理商： | AD9216BCPZRL7-80 |
Preliminary Technical Data
AD9216
EQUIVALENT CIRCUITS
Rev. PrD
Page 13 of 20
6/15/2004
Figure xx.
Equivalent Analog Input Circuit
Figure xx.
Equivalent Digital Output Circuit
Figure xx.
Equivalent Digital Input Circuit
THEORY OF OPERATION
The AD9216 consists of two high performance analog-to-
digital converters (ADCs) that are based on the AD9215
converter core. The dual ADC paths are independent, except for
a shared internal band gap reference source, VREF. Each of the
ADC’s paths consists of a proprietary front end sample-and-
hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The pipelined ADC is divided into three
sections, consisting of a 4-bit first stage followed by five 1.5-
bit stages and a final 3-bit fl ash. Each stage provides sufficient
overlap to correct for fl ash errors in the preceding stages. The
quantized outputs from each stage are combined through the
digital correction logic block into a final 10-bit result. The
pipelined architecture permits the first stage to operate on a
new input sample, while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge of the
respective clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution fl ash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the fl ash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
configured as ac- or dc-coupled in differential or single-ended
modes. The output-staging block aligns the data, carries out the
error correction, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9216 is a differential switched
capacitor, SHA, that has been designed for optimum
performance while processing a differential input signal. The
SHA input accepts inputs over a wide common-mode range. An
input common-mode voltage of mid supply is recommended to
maintain optimal performance.
The SHA input is a differential switched capacitor circuit. In
Figure 4, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
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| AD9218 | 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
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相關代理商/技術參數 |
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| AD9218 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
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| AD9218-105PCB | 制造商:Analog Devices 功能描述:DUAL 10 BIT 105/80/65 MSPS ADC EVAL BD. - Bulk |
| AD9218-65PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
| AD9218BST-105 | 功能描述:IC ADC 10BIT DUAL 105MSPS 48LQFP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
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