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參數資料
| 型號： | AD9222ABCPZRL7-65 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/60頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 65MSPS 64LFCSP |
| 標準包裝： | 750 |
| 位數： | 12 |
| 采樣率（每秒）： | 65M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 8 |
| 功率耗散（最大）： | 950.5mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 16 個單端，單極；8 個差分，單極 |
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Octal, 12-Bit, 40/50/65 MSPS
Serial LVDS 1.8 V A/D Converter
Data Sheet
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2006–2011 Analog Devices, Inc. All rights reserved.
FEATURES
8 ADCs integrated into 1 package
114 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
ENOB = 11.3 bits
SFDR = 80 dBc
Excellent linearity: DNL = ±0.3 LSB (typical),
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar IEEE 1596.3)
Data and frame clock outputs
325 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-to-
digital converter (ADC) with an on-chip sample-and-hold
circuit designed for low cost, low power, small size, and ease of
use. The product operates at a conversion rate of up to 65 MSPS
and is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock output (DCO)
for capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
LVDS
REF
SELECT
AD9222
AGND
VIN – A
VIN + A
VIN – B
VIN + B
VIN – D
VIN + D
VIN – C
VIN + C
SENSE
VREF
AVDD
DRVDD
12
PDWN
REFT
REFB
D – A
D + A
D – B
D + B
D – D
D + D
D – C
D + C
FCO –
FCO +
DCO +
DCO –
CLK+
DRGND
CLK–
SERIAL PORT
INTERFACE
CSB
SCLK/
DTP
SDIO/
ODM
RBIAS
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
ADC
DATA RATE
MULTIPLIER
0.5V
SERIAL
LVDS
VIN – E
VIN + E
VIN – F
VIN + F
VIN – H
VIN + H
VIN – G
VIN + G
12
D – E
D + E
D – F
D + F
D – H
D + H
D – G
D + G
SERIAL
LVDS
SERIAL
LVDS
SERIAL
LVDS
ADC
05967-
001
Figure 1.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of 40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight ADCs are contained in a small,
space-saving package.
2. Low power of 114 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9252 (14-bit).
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| AD9224ARSZRL | IC ADC 12BIT 40MSPS 28SSOP |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9222BCPZ-40 | 制造商:Analog Devices 功能描述:Octal ADC Pipelined 40Msps 12-bit Serial 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述: |
| AD9222BCPZ-50 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 50Msps 12-bit Serial 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:12BIT ADC OCTAL 50MSPS LFCSP-64 |
| AD9222BCPZ-65 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9222BCPZRL7-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Octal, 12-Bit, 40/50 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9222BCPZRL7-50 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 50Msps 12-bit Serial 64-Pin LFCSP EP T/R |
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