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參數資料
| 型號： | AD9223 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| 中文描述： | 完整的12位1.5/3.0/10.0 MSPS的單片的A / D轉換器 |
| 文件頁數： | 12/28頁 |
| 文件大小： | 350K |
| 代理商： | AD9223 |
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AD9221/AD9223/AD9220
REV. D
–12–
other comparator controls internal circuitry which will disable
the reference amplifier if the SENSE pin is tied AVDD. Dis-
abling the reference amplifier allows the VREF pin to be driven
by an external voltage reference.
A2
5k
V
5k
V
5k
V
5k
V
LOGIC
DISABLE
A2
7.5k
V
LOGIC
5k
V
DISABLE
A1
1V
TO
A/D
AD9221/AD9223/AD9220
CAPT
CAPB
VREF
SENSE
REFCOM
A1
Figure 35. Equivalent Reference Circuit
The actual reference voltages used by the internal circuitry of
the AD9221/AD9223/AD9220 appear on the CAPT and CAPB
pins. For proper operation when using the internal or an exter-
nal reference, it is necessary to add a capacitor network to de-
couple these pins. Figure 36 shows the recommended
decoupling network. This capacitive network performs the
following three functions: (1) along with the reference ampli-
fier, A2, it provides a low source impedance over a large fre-
quency range to drive the A/D internal circuitry, (2) it provides
the necessary compensation for A2, and (3) it bandlimits the
noise contribution from the reference. The turn-on time of the
reference voltage appearing between CAPT and CAPB is ap-
proximately 15 ms and should be evaluated in any power-
down mode of operation.
0.1
m
F
10
m
F
0.1
m
F
0.1
m
F
CAPT
CAPB
AD9221/
AD9223/
AD9220
Figure 36. Recommended CAPT/CAPB Decoupling Network
The A/D’s input span may be varied dynamically by changing
the differential reference voltage appearing across CAPT and
CAPB symmetrically around 2.5 V (i.e., midsupply). To change
the reference at speeds beyond the capabilities of A2, it will be
necessary to drive CAPT and CAPB with two high speed, low
noise amplifiers. In this case, both internal amplifiers (i.e., A1
and A2) must be disabled by connecting SENSE to AVDD and
VREF to REFCOM and the capacitive decoupling network
removed. The external voltages applied to CAPT and CAPB
must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4 respec-
tively in which the input span can be varied between 2 V and 5V.
Note that those samples within the pipeline A/D during any
reference transition will be corrupted and should be discarded.
Figure 29. For noise sensitive applications, the excessive band-
width may be detrimental and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
A/D’s input by forming a low-pass filter. Note, however, that
the combination of this series resistance with the equivalent
input capacitance of the AD9221/AD9223/AD9220 should be
evaluated for those time-domain applications that are sensitive
to the input signal’s absolute settling time. In applications where
harmonic distortion is not a primary concern, the series resis-
tance may be selected in combination with the SHA’s nominal
16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.
A better method of reducing the noise bandwidth, while possi-
bly establishing a real pole for an antialiasing filter, is to add
some additional shunt capacitance between the input (i.e.,
VINA and/or VINB) and analog ground. Since this additional
shunt capacitance combines with the equivalent input capaci-
tance of the AD9221/AD9223/AD9220, a lower series resis-
tance can be selected to establish the filter’s cutoff frequency
while not degrading the distortion performance of the device.
The shunt capacitance also acts like a charge reservoir, sinking
or sourcing the additional charge required by the hold capacitor,
C
H
, further reducing current transients seen at the op amp’s
output.
The effect of this increased capacitive load on the op amp driv-
ing the AD9221/AD9223/AD9220 should be evaluated. To
optimize performance when noise is the primary consideration,
increase the shunt capacitance as much as the transient response
of the input signal will allow. Increasing the capacitance too
much may adversely affect the op amp’s settling time, frequency
response, and distortion performance.
REFERENCE OPERATION
The AD9221/AD9223/AD9220 contain an onboard bandgap
reference that provides a pin-strappable option to generate either a
1 V or 2.5 V output. With the addition of two external resistors,
the user can generate reference voltages other than 1 V and
2.5 V. Another alternative is to use an external reference for
designs requiring enhanced accuracy and/or drift performance.
See Table II for a summary of the pin-strapping options for the
AD9221/AD9223/AD9220 reference configurations.
Figure 35 shows a simplified model of the internal voltage refer-
ence of the AD9221/AD9223/AD9220. A pin-strappable refer-
ence amplifier buffers a 1 V fixed reference. The output from
the reference amplifier, A1, appears on the VREF pin. The
voltage on the VREF pin determines the full-scale input span of
the A/D. This input span equals,
Full-Scale Input Span = 2
×
VREF
The voltage appearing at the VREF pin as well as the state of
the internal reference amplifier, A1, are determined by the volt-
age appearing at the SENSE pin. The logic circuitry contains
two comparators which monitor the voltage at the SENSE pin.
The comparator with the lowest set point (approximately 0.3 V)
controls the position of the switch within the feedback path of
A1. If the SENSE pin is tied to REFCOM, the switch is con-
nected to the internal resistor network thus providing a VREF
of 2.5 V. If the SENSE pin is tied to the VREF pin via a short
or resistor, the switch is connected to the SENSE pin. A short
will provide a VREF of 1.0 V while an external resistor network
will provide an alternative VREF between 1.0 V and 2.5 V. The
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| AD9223ARSZ | 功能描述:IC ADC 12BIT 3.0MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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