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參數資料
| 型號： | AD9223AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters |
| 中文描述： | 1-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MS-013AE, SOIC-28 |
| 文件頁數： | 13/28頁 |
| 文件大小： | 350K |
| 代理商： | AD9223AR |
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AD9221/AD9223/AD9220
REV. D
–13–
Table I. Analog Input Configuration Summary
Input
Connection
Single-Ended
Input
Span (V)
2
Input Range (V)
VINA
1
0 to 2
Figure
#
39, 40
Coupling
DC
VINB
1
1
Comments
Best for stepped input response applications, suboptimum
THD and noise performance, requires
±
5 V op amp.
2
×
VREF
0 to
2
×
VREF
VREF
39, 40
Same as above but with improved noise performance due to
increase in dynamic range. Headroom/settling time require-
ments of
±
5 V op amp should be evaluated.
5
0 to 5
2.5
39, 40
Optimum noise performance, excellent THD performance,
Requires op amp with VCC > +5 V due to headroom issue.
2
×
VREF
2.5 – VREF
to
2.5 + VREF
2.5
50
Optimum THD performance with VREF = 1, noise
performance improves while THD performance degrades as
VREF increases to 2.5 V. Single supply operation (i.e., +5 V) for
many op amps.
Single-Ended
AC
2 or
2
×
VREF
0 to 1 or
0 to 2
×
VREF
1 or VREF
41
Suboptimum ac performance due to input common-mode
level not biased at optimum midsupply level (i.e., 2.5 V).
5
0 to 5
2.5
41
Optimum noise performance, excellent THD performance,
ability to use
±
5 V op amp.
2
×
VREF
2.5 – VREF
to
2.5 + VREF
2.5
42
Flexible input range, Optimum THD performance with
VREF = 1. Noise performance improves while THD perfor-
mance degrades as VREF increases to 2.5 V. Ability to use
+5 V or
±
5 V op amp.
Differential
(via Transformer)
AC
2
2 to 3
3 to 2
45
Optimum full-scale THD and SFDR performance well be-
yond the A/Ds Nyquist frequency. Preferred mode for under-
sampling applications.
2
×
VREF
2.5 – VREF/2
to
2.5 + VREF/2
2.5 + VREF/2
to
2.5 – VREF/2
45
Same as 2 V to 3 V input range with the exception that full-scale
THD and SFDR performance can be traded off for better noise
performance. Refer to discussion in AC Coupling and Interface
Issue section and Simple AC Interface section.
5
1.75 to 3.25
3.25 to 1.75
45
Optimum Noise performance. Also, the optimum THD and
SFDR performance for “less than” full-scale signals (i.e.,
–6 dBFS). Refer to discussion in AC Coupling and Interface
Issue section and Simple AC Interface section.
NOTE
1
VINA and VINB can be interchanged if signal inversion is required.
Table II. Reference Configuration Summary
Reference
Operating Mode
Input Span (VINA–VINB)
(V p-p)
Required VREF (V)
Connect
To
INTERNAL
INTERNAL
INTERNAL
2
5
2
≤
SPAN
≤
5 AND
SPAN = 2
×
VREF
2
≤
SPAN
≤
5
1
2.5
1
≤
VREF
≤
2.5 AND
VREF = (1 + R1/R2)
1
≤
VREF
≤
2.5
SENSE
SENSE
R1
R2
VREF
REFCOM
VREF AND SENSE
SENSE AND REFCOM
EXTERNAL
(NONDYNAMIC)
SENSE
VREF
AVDD
EXT. REF.
EXTERNAL
(DYNAMIC)
2
≤
SPAN
≤
5
CAPT and CAPB
Externally Driven
SENSE
VREF
EXT. REF.
EXT. REF.
AVDD
REFCOM
CAPT
CAPB
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| AD9223ARS | 制造商:Analog Devices 功能描述:ADC Single Pipelined 3Msps 12-bit Parallel 28-Pin SSOP 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
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| AD9223ARSZ | 功能描述:IC ADC 12BIT 3.0MSPS 28-SSOP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:microPOWER™ 位數:8 采樣率（每秒）:1M 數據接口:串行，SPI? 轉換器數目:1 功率耗散（最大）:- 電壓電源:模擬和數字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應商設備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數目和類型:8 個單端，單極 產品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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