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| 型號(hào)： | AD9229BCP-50 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Quad 12-Bit, 50/65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48 |
| 封裝： | MO-220-VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 471K |
| 代理商： | AD9229BCP-50 |
Prelimnary Technical Data
AD9229
Rev. PrF |Page 9 of 15
Oct. 6, 2003
Definitions
ANALOG BANDWIDTH
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
APERTURE DELAY
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input is
sampled.
APERTURE UNCERTAINTY (JITTER)
The sample-to-sample variation in aperture delay.
CROSSTALK
Coupling onto one channel being driven by a low level (-40 dBFS)
signal when the adjacent interfering channel is driven by a full-
scale signal.
DIFFERENTIAL ANALOG INPUT RESISTANCE,
DIFFERENTIAL ANALOG INPUT CAPACITANCE, AND
DIFFERENTIAL ANALOG INPUT IMPEDANCE
The real and complex impedances measured at each analog input
port. The resistance is measured statically and the capacitance and
differential input impedances are measured with a network
analyzer.
DIFFERENTIAL ANALOG INPUT VOLTAGE RANGE
The peak to peak differential voltage that must be applied to the
converter to generate a full scale response. Peak differential voltage
is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees out
of phase. Peak to peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
Then the difference is computed between both peak measurements.
DIFFERENTIAL NONLINEARITY
The deviation of any code width from an ideal 1 LSB step.
EFFECTIVE NUMBER OF BITS
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
02
.
76
.
dB
SNR
ENOB
MEASURED
=
ENCODE PULSE WIDTH/DUTY CYCLE
Pulse width high is the minimum amount of time that the
ENCODE pulse should be left in logic “1” state to achieve rated
performance; pulse width low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing tENCH in text. At a give clock rate, these specs define an
acceptable Encode duty cycle.
FULL SCALE INPUT POWER
Expressed in dBm. Computed using the following equation:
=
001
.
log
10
2
Input
Fullscale
Z
Fullscale
V
Power
rms
GAIN ERROR
Gain error is the difference between the measured and ideal full
scale input voltage range of the worst ADC.
GAIN MATCHING
Expressed in %FSR. Computed using the following equation:
%
100
*
2
min
max
min
max
+
=
FSR
FSR
FSR
FSR
ng
GainMatchi
where FSR
max
is the most positive gain error of the ADCs and
FSR
min
is the most negative gain error of the ADCs.
HARMONIC DISTORTION, SECOND
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
HARMONIC DISTORTION, THIRD
The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.
INTEGRAL NONLINEARITY
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9229BCP-65 | 制造商:Analog Devices 功能描述:- Bulk |
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| AD9229BCPZRL7-50 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9230 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210/250 MSPS 1.8 V A/D Converter |
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