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參數資料
| 型號： | AD9235BRU-20 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 20/40/65 MSPS 3 V A/D Converter |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-153-AE, TSSOP-28 |
| 文件頁數： | 7/32頁 |
| 文件大小： | 1181K |
| 代理商： | AD9235BRU-20 |
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REV. B
–7–
AD9235
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (t
A
)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Jitter (t
J
)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs 1/2 LSB before the first code transi-
tion. Positive full scale is defined as a level 1 1/2 LSBs beyond
the last code transition. The deviation is measured from the
middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096 codes
must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value 1/2 LSB
below VIN+ = VIN–. Offset error is defined as the deviation of
the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur
at an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies the
maximum change from the initial (25
°
C) value to the value at
T
MIN
or T
MAX
.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum
limit.
Total Harmonic Distortion (THD)
*
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Signal-to-Noise and Distortion (SINAD)
*
The ratio of the rms signal amplitude (set 0.5 dB below full scale)
to the rms value of the sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
The effective number of bits for a device for sine wave inputs at
a given input frequency can be calculated directly from its mea-
sured
SINAD
using the following formula
N
Signal-to-Noise Ratio (SNR)
*
The ratio of the rms signal amplitude (set at 0.5 dB below
full scale) to the rms value of the sum of all other spectral
components below the Nyquist frequency, excluding the first six
harmonics and dc.
Spurious Free Dynamic Range (SFDR)
*
The difference in dB between the rms amplitude of the input signal
and the peak spurious signal.
Two-Tone SFDR
*
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle
Pulsewidth high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated perfor-
mance. Pulsewidth low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these speci-
fications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (t
PD
)
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input after
a transition from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
SINAD
(
=
1 76 6 02
.
.
*
AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9235BRU-20Z | 制造商:Analog Devices 功能描述:ADC 3V 12BIT 20MSPS 0.8LSB 制造商:Analog Devices 功能描述:ADC, 3V, 12BIT, 20MSPS, 0.8LSB, 28TSSOP; Resolution (Bits):12bit; Sampling Rate:20MSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:3.6V; Supply Current:30mA; Digital IC Case Style:TSSOP; No. of Pins:28; ;RoHS Compliant: Yes |
| AD9235BRU-40 | 功能描述:IC ADC 12BIT 40MSPS 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9235BRU-65 | 功能描述:IC ADC 12BIT 65MSPS 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9235BRURL7-20 | 功能描述:IC ADC 12BIT SGL 20MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
| AD9235BRURL7-40 | 功能描述:IC ADC 12BIT SGL 40MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率（每秒）:3M 數據接口:- 轉換器數目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:- |
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