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參數資料
型號: AD9238BST-65
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 12-Bit, 20/40/65 MSPS Dual A/D Converter
中文描述: 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP64
封裝: LEAD FREE, MS-026-BBD, LQFP-64
文件頁數: 7/24頁
文件大小: 1737K
代理商: AD9238BST-65
AD9238
–7–
TERMINOLOGY
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
The variation in aperture delay for successive samples, which is
manifested as noise on the input to the A/D converter.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed no
missing codes to 12-bit resolution indicates that all 4096 codes
must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
1/2 LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last transition should occur at an
analog value 1 1/2 LSB below the nominal full scale. Gain error
is the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
T
MIN
or T
MAX
.
Power Supply Rejection
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
Total Harmonic Distortion (THD)
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal, expressed as a
percentage or in decibels relative to the peak carrier signal (dBc).
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
The ratio of the rms value of the measured input signal to the rms
sum of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc. The value for S/N+D is
expressed in decibels relative to the peak carrier signal (dBc).
Effective Number of Bits (ENOB)
Using the following formula:
ENOB
SINAD
=
(
–1 76 6 02
/ .
effective number of bits for a device for sine wave inputs at a
given input frequency can be calculated directly from its
measured
SINAD
.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the rms
sum of all other spectral components below the Nyquist frequency,
excluding the first six harmonics and dc. The value for SNR is
expressed in decibels relative to the peak carrier signal (dBc).
Spurious Free Dynamic Range (SFDR)
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (f
CLOCK
/2), this is often referred to as
Nyquist sampling.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be aliased
down into the first Nyquist zone (DC – f
CLOCK
/2) on the output
of the ADC. Care must be taken that the bandwidth of the sam-
pled signal does not overlap Nyquist zones and alias onto itself.
Nyquist sampling performance is limited by the bandwidth of the
input SHA and clock jitter (jitter adds more noise at higher input
frequencies).
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the A/D con-
verter to reacquire the analog input after a transient from 10%
above positive full scale to 10% above negative full scale, or from
10% below negative full scale to 10% below positive full scale.
Crosstalk
Coupling onto one channel being driven by a (–0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both direct
coupling and mixing components.
REV. A
相關PDF資料
PDF描述
AD9238BSTRL-20 12-Bit, 20/40/65 MSPS Dual A/D Converter
AD9238BSTRL-40 12-Bit, 20/40/65 MSPS Dual A/D Converter
AD9238BSTRL-65 12-Bit, 20/40/65 MSPS Dual A/D Converter
AD9240 Complete 14-Bit, 10 MSPS Monolithic A/D Converter
AD9240AS Complete 14-Bit, 10 MSPS Monolithic A/D Converter
相關代理商/技術參數
參數描述
AD9238BST-65PCB 制造商:Analog Devices 功能描述:Evaluation Board For AD9238 Dual A/D Converter ,12-Bit, 20 MSPS/40 MSPS/65 MSPS 制造商:Rochester Electronics LLC 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk
AD9238BST-65PCBZ 制造商:Analog Devices 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk
AD9238BSTRL-20 制造商:Rochester Electronics LLC 功能描述:DUAL 12 BIT 3V CMOS 20/40/65 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:
AD9238BSTRL-40 功能描述:IC ADC 12BIT DUAL 40MSPS 64-LQFP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率(每秒):3M 數據接口:- 轉換器數目:- 功率耗散(最大):- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:-
AD9238BSTRL-65 功能描述:IC ADC 12BIT DUAL 65MSPS 64-LQFP RoHS:否 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數:12 采樣率(每秒):3M 數據接口:- 轉換器數目:- 功率耗散(最大):- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應商設備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數目和類型:-
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