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參數資料
型號: AD9244-EVAL
廠商: Analog Devices, Inc.
英文描述: 14-Bit, 40/65 MSPS Monolithic A/D Converter
中文描述: 14位,六十五分之四十MSPS的單片機的A / D轉換器
文件頁數: 7/36頁
文件大小: 1845K
代理商: AD9244-EVAL
REV. A
AD9244
–7–
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
D
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AGND
AGND
AVDD
AVDD
AGND
CLK–
CLK+
NIC
OEB
D0 (LSB)
D1
D2
D
D
D
D
D
D
D
D
D
D
D
D11
D12
D13 (MSB)
OTR
DRVDD
DGND
AVDD
AGND
AGND
AVDD
DFS
SENSE
V
V
V
C
N
D
R
R
R
R
R
V
AD9244
TOP VIEW
(NOT TO SCALE)
PIN FUNCTION DESCRIPTIONS
Description
Pin No.
Mnemonic
1, 2, 5, 32, 33
3, 4, 31, 34
6, 7
8, 44
9
10
11
13, 16
21,
24
26
14, 22, 30
15, 23, 29
27
28
35
36
37
38
39
42
43
AGND
AVDD
CLK
, CLK+
NIC
OEB
D0 (LSB)
D1
D3, D4
D9,
D10
D12
DGND
DRVDD
D13 (MSB)
OTR
DFS
SENSE
VREF
REFGND
REFB, REFT
DCS
Analog Ground.
Analog Supply Voltage.
Differential Clock Inputs.
No Internal Connection.
Digital Output Enable (Active Low).
Least Significant Bit, Digital Output.
Digital Outputs.
Digital Ground.
Digital Supply Voltage.
Most Significant Bit, Digital Output.
Out-of-Range Indicator (Logic 1 indicates OTR).
Data Format Select. Connect to AGND for straight binary, AVDD for twos complement.
Internal Reference Control.
Internal Reference.
Reference Ground.
Internal Reference Decoupling.
50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND
for external control of both clock edges.
Common-Mode Reference (0.5
×
AVDD).
Differential Analog Inputs.
Internal Bias Decoupling.
45
46, 47
48
CML
VIN+, VIN
VR
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參數描述
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