- 您現在的位置：買賣IC網 > PDF目錄373962 > AD9244BST-40 (ANALOG DEVICES INC) 14-Bit, 40/65 MSPS Monolithic A/D Converter PDF資料下載
參數資料
| 型號： | AD9244BST-40 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 40/65 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數： | 8/36頁 |
| 文件大小： | 1845K |
| 代理商： | AD9244BST-40 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
REV. A
–8–
AD9244
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak-to-peak differential is computed by rotating
the input phase 180
°
and taking the peak measurement again.
Then the difference is found between the two peak measurements.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes must be present over all operating ranges.
Dual Tone SFDR
*
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Effective Number of Bits (ENOB)
The effective number of bits for a device for sine wave inputs at
a given input frequency can be calculated directly from its mea-
sured SINAD using the following formula:
=
(
Gain Error
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last code transition should occur
at an analog value 1 1/2 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Common-Mode Rejection Ratio (CMRR)
Common-mode (CM) signals appearing on VIN+ and VIN
–
are
ideally rejected by the differential front end of the ADC. With a
full-scale CM signal driving both VIN+ and VIN
–
, CMRR is the
ratio of the amplitude of the full-scale input CM signal to the
amplitude of signal that is not rejected, expressed in dBFS.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be aliased
down into the first Nyquist zone (DC
–
f
CLOCK
/2) on the output
of the ADC. Care must be taken that the bandwidth of the
N
SINAD
)
–
.
1 76
/6 02
sampled signal does not overlap Nyquist zones and alias onto
itself. Nyquist sampling performance is limited by the band-
width of the input SHA and clock jitter (noise caused by jitter
increases as the input frequency increases).
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (f
CLOCK
/2), this is often referred to as
Nyquist sampling.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at its
minimum limit to the value with the supply at its maximum limit.
Signal-to-Noise-and-Distortion (SINAD)
*
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist fre-
quency, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
*
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist fre-
quency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
*
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25
°
C) value to the value
at T
MIN
or T
MAX
.
Total Harmonic Distortion (THD)
*
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Offset Error
The major carry transition should occur for an analog value
1/2 LSB below VIN+ = VIN
–
. Offset error is defined as the
deviation of the actual transition from that point.
*
AC specifications may be reported in dBc (degrades as signal levels are lowered) or
in dBFS (always related back to converter full scale).
相關PDF資料 |
PDF描述 |
|---|---|
| AD9245 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCP-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCPRL7-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCPZ-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
| AD9245BCPZRL7-80 | 14-Bit, 80 MSPS, 3 V A/D Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9244BST-40Z | 制造商:Analog Devices 功能描述:ADC 14BIT 40MSPS 1.3LSB 48 制造商:Analog Devices 功能描述:ADC, 14BIT, 40MSPS, 1.3LSB, 48LQFP; Resolution (Bits):14bit; Sampling Rate:40MSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:64mA; Digital IC Case Style:LQFP; No. of Pins:48; Input;RoHS Compliant: Yes |
| AD9244BST-65 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 65Msps 14-bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14 BIT 40/65 MSPS IF SAMPLIGN ADC - Bulk 制造商:Analog Devices 功能描述:IC 14BIT ADC SMD 9244 LQFP48 制造商:Analog Devices 功能描述:ADC,AD9244B 14bit 65MSPS LQFP |
| AD9244BSTRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9244BSTRL-65 | 制造商:Analog Devices 功能描述:Single ADC Pipelined 65Msps 14-bit Parallel 48-Pin LQFP T/R |
| AD9244BSTZ40 | 制造商:Analog Devices 功能描述: |
發布緊急采購，3分鐘左右您將得到回復。