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參數資料
| 型號： | AD9248-20PCB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| 中文描述： | 14位，20/40/65 MSPS雙通道的A / D轉換器 |
| 文件頁數： | 18/23頁 |
| 文件大小： | 419K |
| 代理商： | AD9248-20PCB |
AD9248
Preliminary Technical Data
The data format can be selected for either offset binary or twos
complement. This is discussed later in the Data Format section.
Rev. PrE | Page 18 of 23
TIMING
The AD9248 provides latched data outputs with a pipeline
delay of seven clock cycles. Data outputs are available one
propagation delay (t
) after the rising edge of the clock signal.
Refer to Figure 2 for a detailed timing diagram.
The internal duty cycle stabilizer can be enabled on the
AD9248-65 using the DCS pin. This provides a stable 50%
duty cycle to internal circuits.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9248.
These transients can detract from the converter’s dynamic
performance. The lowest typical conversion rate of the AD9248
is 1 MSPS. At clock rates below 1 MSPS, dynamic
performance may degrade.
Figure xx. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
DATA FORMAT
The AD9248 data output format can be configured for either
twos complement or offset binary. This is controlled by the
Data Format Select pin (DFS). Connecting DFS to AGND will
produce offset binary output data. Conversely, connecting DFS
to AVDD will format the output data as twos complement.
The output data from the dual A/D converters can be
multiplexed onto a single 12-bit output bus. The multiplexing is
accomplished by toggling the MUX_SELECT bit, which
directs channel data to the same or opposite channel data port.
When MUX_SELECT is logic high, the Channel A data is
directed to Channel A output bus, and Channel B data is
directed to the Channel B output bus. When MUX_SELECT is
logic low, the channel data is reversed, i.e., Channel A data is
directed to the Channel B output bus and Channel B data is
directed to the Channel A output bus. By toggling the
MUX_SELECT bit, multiplexed data is available on either of
the output data ports.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT bit. After the
MUX_SELECT rising edge, either data port will have the data
for its respective channel; after the falling edge, the alternate
channel’s data will be placed on the bus. Typically, the other
unused bus would be disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure xx shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel's power-
down pin must remain low.
相關PDF資料 |
PDF描述 |
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| AD9248-40PCB | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248-65PCB | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCPZ-20 | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCPZ-40 | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCPZ-65 | 14-Bit, 20/40/65 MSPS Dual A/ D Converter |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9248-40PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248-65PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 20/40/65 MSPS Dual A/ D Converter |
| AD9248BCP-20EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR DUAL A/D CONVERTER ;14-BIT, 20 MSPS/40 MSPS/65 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR DUAL A/D CNVRTR ;14BIT, 20 MSPS/40 MSPS/65 MSPS - Bulk |
| AD9248BCP-20EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For Dual A/D Converter ;14-Bit, 20 MSPS/40 MSPS/65 MSPS 制造商:Analog Devices 功能描述:EVAL BD FOR DUAL A/D CNVRTR ;14BIT, 20 MSPS/40 MSPS/65 MSPS - Bulk 制造商:Analog Devices 功能描述:A/D Converter (A-D) IC |
| AD9248BCP-40EB | 制造商:Analog Devices 功能描述:EVAL BD FOR DUAL A/D CNVRTR ;14BIT, 20 MSPS/40 MSPS/65 MSPS - Bulk |
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