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參數資料
| 型號： | AD9260EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| 中文描述： | 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數轉換器 |
| 文件頁數： | 8/36頁 |
| 文件大小： | 572K |
| 代理商： | AD9260EB |
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–8–
REV. B
AD9260
–
SPECIFICATIONS
DIGITAL SPECIFICATIONS
Parameter
CLOCK
1
AND LOGIC INPUTS
High-Level Input Voltage
(DVDD = +5 V)
(DVDD = +3 V)
Low-Level Input Voltage
(DVDD = +5 V)
(DVDD = +3 V)
High-Level Input Current (V
IN
= DVDD)
Low-Level Input Current (V
IN
= 0 V)
Input Capacitance
AD9260
Units
+3.5
+2.1
V min
V max
+1.0
+0.9
±
10
±
10
5
V min
V max
μ
A max
μ
A max
pF typ
LOGIC OUTPUTS (with DRVDD = 5 V)
High-Level Output Voltage (I
OH
= 50
μ
A)
High-Level Output Voltage (I
OH
= 0.5 mA)
Low-Level Output Voltage
2
(I
OL
= 0.3 mA)
Low-Level Output Voltage (I
OL
= 50
μ
A)
Output Capacitance
+4.5
+2.4
+0.4
+0.1
5
V min
V min
V max
V max
pF typ
LOGIC OUTPUTS (with DRVDD = 3 V)
High-Level Output Voltage (I
OH
= 50
μ
A)
Low-Level Output Voltage (I
OL
= 50
μ
A)
+2.4
+0.7
V min
V max
NOTES
1
Since CLK is referenced to AVDD, +5 V logic input levels only apply.
2
The AD9260 is not guaranteed to meet V
OL
= 0.4 V max for standard TTL load of I
OL
= 1.6 mA.
Specifications subject to change without notice.
ANALOG INPUT
INPUT CLOCK
DATA OUTPUT
DAV
S1
S2
t
DS
t
H
t
CH
t
CL
t
DAV
t
DI
t
C
READ
CS
t
OD
t
OE
Figure 4a. Timing Diagram
INPUT CLOCK
RESET
DAV
t
RES-DAV
t
CLK-DAV
Figure 4b.
RESET
Timing Diagram
(AVDD = +5 V, DVDD = +5 V, T
MIN
to T
MAX
unless otherwise noted)
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|---|---|
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
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