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參數資料
| 型號： | AD9445-IF-PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 105/125 MSPS, IF Sampling ADC |
| 中文描述： | 14位，一百二十五分之一百○五MSPS的，中頻采樣ADC |
| 文件頁數： | 6/40頁 |
| 文件大小： | 965K |
| 代理商： | AD9445-IF-PCB |
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AD9445
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, R
LVDS_BIAS
= 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR)
1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)
V
OD
Differential Output Voltage
2
V
OS
Output Offset Voltage
CLOCK INPUTS (CLK+, CLK)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
1
Output voltage levels measured with 5 pF load on each output.
2
LVDS R
TERM
= 100 Ω.
Rev. 0 | Page 6 of 40
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
2.0
10
2
3.25
247
1.125
0.2
1.3
1.5
1.1
1.4
2
AD9445BSVZ-125
Min
Typ
2.0
10
2
3.25
247
1.125
0.2
1.3
1.5
1.1
1.4
2
Unit
V
V
μA
μA
pF
V
V
mV
V
V
V
kΩ
pF
Max
0.8
200
+10
0.2
545
1.375
1.6
1.7
Max
0.8
200
+10
0.2
545
1.375
1.6
1.7
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High
1
(t
CLKH
)
CLK Pulse Width Low
1
(t
CLKL
)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (t
PD
)
2
(Dx, DCO+)
Output Propagation Delay—LVDS (t
PD
)
3
(Dx+), (t
CPD
)
3
(DCO+)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (Jitter, t
J
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
105
9.5
3.8
3.8
3.35
2.1
3.6
13
60
AD9445BSVZ-125
Min
Typ
125
8.0
3.2
3.2
3.35
2.3
3.6
13
60
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
fsec
rms
Max
10
4.8
Max
10
4.8
1
With duty cycle stabilizer (DCS) enabled.
2
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
3
LVDS R
TERM
= 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
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相關代理商/技術參數 |
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|---|---|
| AD9445XSVZ-105 | 制造商:Analog Devices 功能描述:14-BIT ADC - Trays |
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| AD9446-100LVDS | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 80/100 MSPS ADC |
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