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參數(shù)資料
| 型號(hào)： | AD9483KS-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Triple 8-Bit, 140 MSPS A/D Converter |
| 中文描述： | 3-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | HEAT SINK, PLASTIC, MQFP-100 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大小： | 319K |
| 代理商： | AD9483KS-100 |
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AD9483
–15–
REV. A
Data Sync
The Data Sync input, DS, is required to be driven for most
applications to guarantee at which output port a given sample
will appear.
When DS is held high, the ADC data outputs and clock
outputs do not switch—they are held static
. Synchronization is
accomplished by the assertion (falling edge) of DS, within the
timing constraints T
SDS
and T
HDS
relative to an encode rising
edge. (On initial synchronization T
HDS
is not relevant.) If DS
falls T
SDS
before a given encode rising edge N, the analog value
at that point in time will be digitized and available at Port A five
cycles later (interleaved mode). The very next sample, N+l, will
be sampled by the next rising encode edge and available at Port
B five cycles after that encode edge (interleaved mode). In dual
parallel mode the A port has a six cycle latency, the B port has a
five cycle latency as described in Demuxed Outputs Mode section.
DS can be asserted once per video line if desired by using the
horizontal sync signal (HSYNC). The start of HSYNC should
occur after the end of active video by at least the chip latency.
The HSYNC front porch is usually much greater than this in a
typical SXGA system. If this is true in a given system then DS
can be reset high by the HSYNC leading edge (the samples at
that point should not be required in a typical system). DS can
then be reasserted (brought low), by triggering from HSYNC
trailing edge—observing T
SDS
of the next rising encode edge.
The first pixel data (on A Port) would be available five cycles
after the first rising encode after HSYNC goes high.
It is possible to use the phase of the data clock outputs and
software programming to accommodate situations where DS is
not driven. The data clock outputs (CLKOUT and
CLKOUT
)
can be used to determine when data is valid on the output ports.
In these cases DS should be grounded and
DS
left floating or
connected to V
CC
. If CLKOUT was low when a given sample
was taken, the digitized value will be available on Port A, five
cycles later. Data Sync has no effect when Single Channel
Mode is selected, it should be grounded
Figure 2 shows how to use DS properly. The DS rising edge
does not have any special timing requirements except that no
data will come out of either port while it is held HIGH. The
falling edge of DS must, however, meet a minimum setup-and-
hold time with respect to the rising edge of ENCODE.
Single Channel Outputs Mode
In Single Channel mode, (Pin 74 OMS = HIGH), the timing of
the AD9483 is similar to any high speed ADC (Figure 1). A
sample is taken on every rising edge of ENCODE, and the re-
sulting data is produced on the output pins following the fourth
rising edge of ENCODE after the sample was taken, (four pipe-
line delays). The output data are valid t
PD
after the rising edge
of ENCODE, and remain valid until at least t
V
after the next
rising edge of ENCODE.
The maximum conversion rate in the mode should be limited to
100 MSPS. This is recommended because the guaranteed out-
put data valid time minus the propagation delay is only 4 ns at
100 MSPS. This is about as fast as standard logic is able to capture
the data with reasonable design margins. The AD9483 will
operate faster in this mode if the user is able to capture the data.
When operating in single channel mode, all data comes out the
A Ports while the B Ports are held static in a random state.
Data Clock Outputs
The data clock outputs will switch at two potential frequencies.
In Single Channel mode, where all data comes out of Port A
at the full ENCODE rate, the data clock outputs switch at the
same frequency as the ENCODE. In Dual Channel mode,
where the data alternates between the two ports, each of which
operate at 1/2 the full ENCODE rate, the data clock outputs
also switch at 1/2 the full ENCODE rate.
The data clock outputs have two potential purposes. The first is
to act as a latch signal for capturing output data. In order to do
this, simply drive the data latches with the appropriate data
clock output. The second use is in Dual Channel data mode to
help determine out of which data port data will come out. Refer
to Figure 2 for a complete timing diagram, but in this mode, a
rising edge on data clock will correspond to data switching on
data Port B.
LAYOUT AND BYPASSING CONSIDERATIONS
Proper high speed layout and bypassing techniques should be
used with the AD9483. Each V
CC
and V
DD
power pin should be
bypassed as close to the pin as possible with a 0.01
μ
F to 0.1
μ
F
capacitor Also, one 10
μ
F capacitor to ground should be used
per supply per board. The VREF OUT pin and each of the
three VREF IN pins should also be bypassed with a 0.01
μ
F to
0.1
μ
F capacitor to ground.
A single, substantial, low impedance ground plane should be
place under and around the AD9483. Try to maximize the
distance between the sensitive analog signals, (AIN, VREF),
and the digital signals. Capacitive loading on the digital outputs
should be kept to a minimum. This can be facilitated by keeping
the traces short and in the case of the clock outputs by driving
as few other devices as possible. Socketing the AD9483 should
also be avoided. Try to match trace lengths of similar signals to
avoid mismatches in propagation delays, (the encode inputs,
analog inputs, digital outputs).
POWER SUPPLIES
At power up, V
CC
must come up before V
DD
. V
CC
is considered
the converter supply, nominally 5.0 V (
±
5.0%) V
DD
is consider
output power supply, nominally 3.3 V (
±
10%) or 5.0 V (
±
5%).
At power off, V
DD
must turn off first. Failure to observe the
correct power supply sequencing many damage this device.
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