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參數(shù)資料
| 型號： | AD9500 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | 數(shù)字可編程延時發(fā)生器 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 131K |
| 代理商： | AD9500 |
AD9500
–10–
REV. D
LAYOUT CONSIDERATIONS
The AD9500 is a precision timing device, and as such high
frequency design techniques must be employed to achieve the
best performance. The use of a low impedance ground plane is
particularly important. Ideally the ground plane should be on
the component side of the layout and extend under the
AD9500, to shield it from system timing signals. Sockets pose a
special problem for a circuit like the AD9500 because of the
additional inter-lead capacitance they create. If sockets must be
used, pin sockets are generally preferred. Power supply decou-
pling is also critical to a high-speed design; a 0.1
μ
F ceramic
capacitor and a 0.01
μ
F mica capacitor for both power supplies
should be very effective. DAC threshold stability can be improved
by decoupling the OFFSET ADJUST pin to +5.0 V (note that this
will lengthen the DAC settling time, t
DAC
)
DELAY OFFSET ADJUSTMENTS
As the full-scale delay is increased, a component of the mini-
mum propagation delay also increases. This is caused by the
additional time required by the ramp (now with a much “flatter”
slope) to fall below the DAC threshold corresponding to the
minimum propagation delay (t
PD
). One means of decreasing the
minimum propagation delay (when the full-scale delay, set by
R
SET
and C
EXT
is large) is to offset the internal DAC threshold
toward the initial ramp levels, thus reducing the time for the
internal ramp to cross the threshold once the AD9500 is triggered.
Figure 11. The Offset Adjust Pin Can Be Used to Match
Several AD9500s
The DAC levels are offset toward the initial ramp level by in-
jecting a small current into the offset adjust pin. Note, however,
that the ramp start-up region is less linear than the later portions
of the ramp, which is the primary reason for the built-in offset.
If the minimum propagation delay is kept above 5 ns (the linear
portion of the ramp), no significant degradation in linearity
should result. This concept can be extended to match the actual
propagation delays of several AD9500s, by injecting or sinking
a small current (<2 mA) into or out of each of the OFFSET
ADJUST pins.
GENERAL PERFORMANCE ENHANCEMENTS
High speed operation is generally more consistent if C
EXT
is
kept small (i.e., no external capacitor) to maintain small dis-
charge time constants. Integral linearity, however, benefits from
larger values of C
EXT
by buffering small system spikes and
surges. Another means of improving integral linearity is to draw
a small current (
≈
200
μ
A) out of the OFFSET ADJUST pin
with a 47 k
pull-down resistor. This has the effect of moving
the internal DAC reference levels into a relatively more linear
region of the ramp. This technique is generally only useful for
small full-scale delay configurations. Its use with larger full-scale
delays will extend the minimum propagation delay (t
PD
). A pull-
up resistor to +5.0 V creates the opposite effect by reducing the
minimum propagation delay (t
PD
) at the expense of increased
reset propagation delay (t
RD
) and degraded linearity (see OFF-
SET matching circuit).
Caution should be used when applying high slew rate data at the
inputs of the AD9500. For data inputs with slew rates in excess
of 1 V/ns, a 100
series resistor should be utilized in the data
path.
An external DAC can be used with the AD9500 for increased
resolution and higher update rates. For the most part, a stan-
dard ECL DAC, operating between +5.0 V and ground, should
work with the AD9500. The output of the external DAC must
be connected to the OFFSET ADJUST pin of the AD9500 with
the internal DAC turned off (D
0
thru D
7
at logic LOW). For
normal operation, the external DAC output should range from
0 mA to –2 mA (sinking).
Figure 12. Operation with External DAC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9500BP | Digitally Programmable Delay Generator |
| AD9500BQ | Digitally Programmable Delay Generator |
| AD9500TE | Digitally Programmable Delay Generator |
| AD9500TQ | Digitally Programmable Delay Generator |
| AD9501JN | Digitally Programmable Delay Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9500BP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9500BP-REEL | 制造商:Analog Devices 功能描述:Digitally Programmable Delay Generator 28-Pin PLCC T/R |
| AD9500BQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9500TE | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9500TQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
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