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參數資料
| 型號： | AD9500BP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 8/11頁 |
| 文件大小： | 131K |
| 代理商： | AD9500BP |
AD9500
–8–
REV. D
APPLICATIONS
The AD9500 is a very versatile device that is not difficult to use.
Essentially there are only a few basic configurations which can
be extended into a number of applications. The TRIGGER and
RESET inputs of the AD9500 can be treated as single ended, or
as differential, which allows the AD9500 to operate with a wide
range of signal sources. The output pulse from the AD9500 can
be reset in one of two ways, either immediately by driving the
RESET inputs with the output itself, or in a delayed mode.
MINIMUM CONFIGURATION
The minimum configuration uses only one of the TRIGGER
inputs. The other is connected to the ECL reference midpoint,
ECL
REF
. This allows the AD9500 to be triggered with standard
10K or 10KH ECL signals. Once a triggering event occurs, the
Q output will go into the logic HIGH state, and the
Q
output
will go into the logic LOW state after the programmed delay.
The Q output is then used to drive the RESET input, causing
the AD9500 to reset itself. The result is a delayed output pulse
which is only as wide as the reset propagation delay (t
RD
).
Figure 5. Single Input–Minimum Timing Configuration
EXTENDED OUTPUT PULSEWIDTHS
The extended pulse configuration is similar to the minimum
configuration. The difference here is that the output pulsewidth
has been extended. Operation is identical in terms of triggering
the AD9500; the functional difference is in the resetting circuit.
In this case the
Q
output is used to drive the
RESET
input
through a resistor/capacitor charging network. The charging
network will cause the signal at the
RESET
input to fall more
slowly, which will extend the output pulsewidth. An added
benefit of the extended pulsewidth configurations is that both
the Q and the
Q
outputs are completely free for other uses.
Q
has limited current drive; the minimum resistance for R
D
should
be 4 k
.
Figure 6. Extended Output Pulsewidth Configuration
MULTICHANNEL DESKEWING
Perhaps the most appropriate use of the AD9500 is in multiple
delay matching applications. Slight differences in impedance
and cable length can create large timing skews within a high-
speed system. Much of this skew can be eliminated by running
each signal through an AD9500. With one line used as a stan-
dard, the programmed delays of the other AD9500s are adjusted
to eliminate the timing skews. With the very fine timing adjust-
ments possible from the AD9500 (as small as 10 ps), nearly any
high-speed system should be able to automatically adjust itself
to extremely tight tolerances.
Figure 7. Multiple Delay Matching
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PDF描述 |
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| AD9500BQ | Digitally Programmable Delay Generator |
| AD9500TE | Digitally Programmable Delay Generator |
| AD9500TQ | Digitally Programmable Delay Generator |
| AD9501JN | Digitally Programmable Delay Generator |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9500BP-REEL | 制造商:Analog Devices 功能描述:Digitally Programmable Delay Generator 28-Pin PLCC T/R |
| AD9500BQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9500TE | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9500TQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Digitally Programmable Delay Generator |
| AD9500XCHIPS UP WAF | 制造商:Analog Devices 功能描述: |
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