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參數資料
| 型號： | AD9501SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Digitally Programmable Delay Generator |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數： | 11/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | AD9501SQ |
AD9501
REV. A
–11–
Analog Settling T ime Measurement
T his circuit, shown in Figure 9, functions in a manner similar to
the digital delay detector; for this application, too, the clock
must be repetitive. As in the delay detector, AD9501 #1 is used
to cancel the propagation delay of AD9501 #2, propagation
delay of the comparators, stray delays, etc. T o accomplish this,
use the calibration procedure described earlier for the digital
delay generator.
T he difference between the two circuits is in the detection
method. T he register of the digital delay is replaced by a win-
dow comparator for the analog settling measurement.
T hreshold voltages V1 and V2 are set for the desired tolerance
around the final value of the DUT output signal. As shown in
the lower portion of the diagram, the output of the detector is
high when the analog output signal of the converter is within the
limits set by V
1
and V
2
.
T herefore, the settling time can be measured by starting the
delay of AD9501 #2 at its maximum setting and decrementing
it until the window comparator goes low. T he difference
between the DAC codes applied to AD9501 #2 and AD9501
#1 is a measure of the settling time of the D/A converter being
tested.
Figure 9. Analog Settling Time Measurement
Layout Considerations
Although the inputs and output of the AD9501 are digital, the
delay is determined by analog circuits. T his makes it critical to
use high speed analog circuit layout techniques to achieve rated
performance.
T he ground plane should be on the component side of the
board and extend under the AD9501 to shield it from digital
switching signals. Most socket assemblies add significant
inter-lead capacitance, and should be avoided whenever pos-
sible. If sockets must be used, individual pin sockets such as
AMP part number 6330808-0 (closed knock-out end) or
6-330808-3 (open end) should be used.
Power supply decoupling is also critical for high speed design; a
0.1
μ
F capacitor should be connected as close as possible to
each supply pin.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9501JQ | Digitally Programmable Delay Generator |
| AD9502 | Hybrid RS-170 Video Digitizer |
| AD9502AM | Hybrid RS-170 Video Digitizer |
| AD9502BM | Hybrid RS-170 Video Digitizer |
| AD9502CM | Hybrid RS-170 Video Digitizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9502 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Hybrid RS-170 Video Digitizer |
| AD9502(RS-170) | 制造商:AD 制造商全稱:Analog Devices 功能描述:Hybrid RS-170 Video Digitizer |
| AD9502AM | 制造商:AD 制造商全稱:Analog Devices 功能描述:Hybrid RS-170 Video Digitizer |
| AD9502AMB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video Generator & Line Lock Circuit |
| AD9502BM | 制造商:AD 制造商全稱:Analog Devices 功能描述:Hybrid RS-170 Video Digitizer |
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