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參數資料
| 型號： | AD9517-2ABCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/80頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.2GHZ VCO 48LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.33GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
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12-Output Clock Generator with
Integrated 2.2 GHz VCO
Data Sheet
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2007–2013 Analog Devices, Inc. All rights reserved.
FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.05 GHz to 2.33 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Each LVDS output can be reconfigured as two 250 MHz
CMOS outputs
Automatic synchronization of all outputs on power-up
Manual output synchronization available
Available in a 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9517-21 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an on-
chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to
2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9517-2 emphasizes low jitter and phase noise to maximize
data converter performance, and it can benefit other applications
with demanding phase noise and jitter requirements.
FUNCTIONAL BLOCK DIAGRAM
REFIN
REF1
REF2
CLK
LF
SW
IT
C
H
O
VER
AND
M
O
NI
T
O
R
PL
L
DIVIDER
AND MUXs
CP
VCO
STATUS
MONITOR
LVPECL
LVDS/CMOS
SERIAL CONTROL PORT
AND
DIGITAL LOGIC
AD9517-2
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
DIV/Φ
06426-
001
Δt
Figure 1.
The AD9517-2 features four LVPECL outputs (in two pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
For applications that require additional outputs, a crystal reference
input, zero-delay, or EEPROM for automatic configuration at
startup, the AD9520 and AD9522 are available. In addition,
a different combination of outputs.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9517-2 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9517-2 is specified for operation over the industrial
range of 40°C to +85°C.
1
AD9517 is used throughout the data sheet to refer to all the members of the
AD9517 family. However, when AD9517-2 is used, it refers to that specific
member of the AD9517 family.
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| AD9517-3A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9517-3A RoHS:是 類別:編程器，開發系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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