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參數資料
型號: AD9540/PCBZ
廠商: Analog Devices Inc
文件頁數: 1/32頁
文件大?。?/td> 0K
描述: BOARD EVAL CLK GEN SYNTH 48LFCSP
設計資源: AD9540 Eval Brd Schematics
AD9540 Eval Brd BOM
AD9540 Gerber Files
標準包裝: 1
主要目的: 計時,時鐘發生器
已用 IC / 零件: AD9540
已供物品:
655 MHz Low Jitter Clock Generator
AD9540
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Excellent intrinsic jitter performance
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1 to 16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable phase/frequency profiles
400 MSPS internal DDS clock speed
48-bit frequency tuning word resolution
14-bit programmable phase offset
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP_VQ package
Programmable charge pump current (up to 4 mA)
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant output driver
APPLICATIONS
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
Agile LO frequency synthesis
Automotive radar
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DVDD DGND
CP_VDD
CP_RSET
CP
REF, AMP
REFIN
CLK1
CHARGE
PUMP
PHASE
FREQUENCY
DETECTOR
M DIVIDER
N DIVIDER
DIVIDER
1, 2, 4, 8
SYNC_IN/STATUS
SYNC, PLL
LOCK
SCLK
SDI/O
SDO
CS
SERIAL
CONTROL
PORT
TIMING AND
CONTROL LOGIC
CLK2
CP_OUT
CLK2
DRV_RSET
OUT0
CML
OUT0
CLK
DIVCLK
S2
S1
S0
PHASE/
FREQUENCY
PROFILES
DDS
IOUT
DAC
DAC_RSET
48
10
14
04947-001
AD9540
Figure 1.
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相關代理商/技術參數
參數描述
AD9540-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9540 ,655 MHZ LOW JITTER CLOCK GEN - Trays
AD9540-VCO/PCBZ 功能描述:BOARD EVAL CLK GEN SYNTH 48LFCSP RoHS:是 類別:編程器,開發系統 >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信,線路接口單元(LIU) 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板,電源,線纜,CD 其它名稱:82EBV2081
AD9542/PCBZ
AD9542BCPZ 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包裝:托盤 零件狀態:在售 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應商器件封裝:64-LFCSP(9x9) 標準包裝:1
AD9542BCPZ-REEL7 功能描述:SYNCHRONIZER & ADAPTIVE CLOCK TR 制造商:analog devices inc. 系列:* 包裝:帶卷(TR) 零件狀態:在售 安裝類型:表面貼裝 封裝/外殼:64-WFQFN 裸露焊盤 供應商器件封裝:64-LFCSP(9x9) 標準包裝:750
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