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參數(shù)資料
| 型號(hào)： | AD9621SQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Wideband Voltage Feedback Amplifier |
| 中文描述： | OP-AMP, 15000 uV OFFSET-MAX, 350 MHz BAND WIDTH, CDIP8 |
| 封裝： | CERDIP-8 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大小： | 305K |
| 代理商： | AD9621SQ |
AD9621
REV. 0
–5–
–
Typical Performance
(R
L
= 100
; A
V
= +1, unless otherwise noted)
P
O
80
60
40
20
0
–20
0
+15
+30
+45
+60
+75
+90
–15
–30
–45
–60
FREQUENCY – Hz
10k
100k
1M
10M
100M
600M
GAIN
PHASE
Figure 4. Open-Loop Gain and
Phase
1
10
2
4
6
20
40
60
FREQUENCY – MHz
d
–50
–60
–70
–80
–90
–100
–110
–120
2nd HARMONIC
RL = 100
2nd HARMONIC
R
L
= 500
3rd HARMONIC
R
L
= 500
V
OUT
= 2V
p-p
3rd HARMONIC
R
L
= 100
Figure 7. Harmonic Distortion
vs. Frequency
+2
0
–2
–4
–6
–8
M
P
+180
+135
+90
+45
0
–45
–90
–135
–180
FREQUENCY – MHz
50
100 150
200
250 300
350
400
450
500
R
LOAD
= 500
R
LOAD
= 50
AV = 1
R
F
= 51
Figure 10. Frequency Response
vs. R
LOAD
FREQUENCY – Hz
10
8
6
4
2
1
10
2
10
3
10
4
10
5
10
6
10
8
6
4
2
1
VOLTAGE
CURRENT
N
H
N
H
Figure 13. Input Spectral Noise
Density
+2
0
–2
–4
–6
–8
M
P
+180
+135
+90
+45
0
–45
–90
–135
–180
FREQUENCY – MHz
50
100
150
200
250 300
350 400 450 500
A
V
= –1
A
V
= –2
Figure 5. Inverting Frequency
Response
1
100
10
FREQUENCY – MHz
I
40
0
20
10
30
50
50
OUT
Figure 8. Third Order Intercept
+0.1
–0.1
–0.04
–0.08
–0.06
+0.02
–0.02
0
+0.04
+0.06
+0.08
50
0
40
30
20
TIME – ns
10
S
V
OUT
= 2V STEP
TEST CIRCUIT
100
6pF
Figure 11. Short-Term Settling
Time
SUPPLY VOLTAGE –
±
Volts
5.5
5.0
4.5
4.0
3.5
O
±
4
3
2
S
27
23
19
VOLTAGE
CURRENT
Figure 14. Output Level and
Supply Current vs. Supply Voltage
+2
0
–2
–4
–6
–8
M
P
+180
+135
+90
+45
0
–45
–90
–135
–180
FREQUENCY – MHz
50
100 150
200
250
300 350
400
450
500
A
V
= 1
A
V
= 2
A
V
= 4
Figure 6. Noninverting Frequency
Response
+20
+45
+70
+25
+30
+35
+40
+50
+55
+60
+65
CMRR
1
10
1G
10M
1M
100k
10k
1k
FREQUENCY – Hz
100
100M
PSRR
P
M
Figure 9. CMRR and PSRR vs.
Frequency
100K
1
10K
1K
100
10
TIME – ns
+0.1
–0.1
–0.04
–0.08
–0.06
+0.02
–0.02
0
+0.04
+0.06
+0.08
S
V
OUT
= 2V STEP
TEST CIRCUIT
100
6pF
+2V
0
MEASURING
POINT
Figure 12. Long-Term Settling Time
0
50
20
10
30
40
30
18
14
22
26
R
S
10
100
10
1
C
LOAD
– pF
R
S
t
S
T
t
SETTLING
51
R
S
1k
C
L
Figure 15. Settling Time vs.
Capacitive Load
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