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| 型號(hào)： | AD9641-155KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/36頁 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR AD9641 |
| 設(shè)計(jì)資源： | AD9641 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
Data Sheet
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2010–2012 Analog Devices, Inc. All rights reserved.
FEATURES
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
GENERAL DESCRIPTION
The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641 is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
ADC
VIN–
VIN+
AGND
AVDD
DUTY CYCLE
STABILIZER
CLK+
CLK–
DRVDD
DIVIDE-BY-1
TO
DIVIDE-BY-8
SYNC
PROGRAMMING DATA
SPI
AD9641
SDIO SCLK CSB
VCM
PDWN
DRGND
DATA RATE
MULTIPLIER
DOUT+
DOUT–
DSYNC+
DSYNC–
DAT
A
S
E
RI
AL
IZ
E
R,
E
NCO
DE
R,
AND
CM
L
DRI
V
E
RS
MULTICHIP
SYNC
09210-
001
Figure 1.
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9641 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of 40°C to +85°C.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
2.
The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
3.
A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
4.
Operation is from a single 1.8 V power supply.
5.
The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), control-
ling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
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| AD9641-80KITZ | 功能描述:BOARD EVAL FOR AD9641 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9641BCPZ-155 | 制造商:Analog Devices 功能描述:14BIT 155MSPS ADC W/JESD204A - Trays 制造商:Analog Devices 功能描述:IC ADC 14BIT SRL 155MSPS 32LFCSP |
| AD9641BCPZ-80 | 功能描述:IC ADC 14BIT SRL 80MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD9641BCPZRL7-155 | 制造商:Analog Devices 功能描述:14BIT 155MSPS ADC W/JESD204A - Tape and Reel 制造商:Analog Devices 功能描述:IC ADC 14BIT SRL 155MSPS 32LFCSP |
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