
–3–
REV. A
ADAD9701
AD9701BQ
T yp
AD9701SQ/SE
T yp
Parameter
T emp
Min
Max
Min
Max
Units
POWER SUPPLY
13
Supply Current (–5.2 V)
+25
°
C
Full
+25
°
C
Full
140
160
160
140
160
160
mA
mA
mW
mV/V
Nominal Power Dissipation
Power Supply Rejection Ratio
14
728
3
728
3
6
6
NOT ES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under
any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
T ypical thermal impedance . . .
22-Pin Ceramic
θ
JA
= 64
°
C/W;
θ
JC
= 16
°
C/W
28-Pin Ceramic LCC
θ
= 70
°
C/W
θ
= 21
°
C/W
3
SYNC, BLANK ING, and REFERENCE WHIT E are inactive (Logic “1”). I
SET
≈
1.26 V/R
SET
.
4
All bits at logic HIGH.
5
All values are relative to full-scale output after being normalized to nominal value. T ypical variation in full-scale output from device to device can reach
±
10%, for a
fixed R
resistor.
6
T he effect of 10% BRIGHT algebraically adds to the output waveform.
7
T he output level with BLANK ING active (Logic “0”) is determined by the setup control level.
8
In normal operation, the BLANK ING input is activated (Logic “0”) prior to or in conjunction with the SYNC input. T he effect of the SYNC output is relative to the
setup level.
9
Measured from edge of ST ROBE to 50% transition point of the output signal.
10
Measured with full-scale change in output level, from the 10% transition level to within
±
0.2% of the final output value.
11
Measured from 10% to 90% transition point for full-scale step output.
12
An IRE unit is 1% of the Grey Scale (GS range) with a 0 IRE setup level.
13
Supply Voltage should remain stable within
±
5% for normal operation.
14
Measured at
±
5% of –V
S
.
Specifications subject to change without notice.
DIGIT AL INPUT S VS. ANALOG OUT PUT
Bit
1
Bit
2
Bit
3
Bit
4
Bit
5
Bit
6
Bit
7
Bit
8
10%
Bright
Ref.
White
Comp.
Sync
Analog
Output (mV)
Blanking
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
–71
–320
–637.5
–708.5
0
–71
–637.50
1
–690.75
2
–708.50
3
–779.50
4
–922.50
1
–975.75
2
–993.50
3
–1064.50
4
–993.50
1
–1046.75
2
–1064.50
3
–1135.50
4
NOT ES
1
Setup (Pin 21) grounded (0 IRE units).
2
Setup (Pin 21) open (7.5 IRE units).
3
Setup (Pin 21) to –5.2 V through 1 k (0 IRE units).
4
Setup (Pin 21) to –5.2 V (20 IRE units).
ORDE RING GUIDE
T emperature
Range
Package
Option*
Device
Description
AD9701BQ
AD9701SE
AD9701SQ
–25
°
C to +85
°
C
–55
°
C to +125
°
C
–55
°
C to +125
°
C
22-Pin DIP, Industrial T emperature
28-Pin LCC, Extended T emperature
22-Pin DIP, Extended T emperature
Q-22
E-28A
Q-22
*E = Leadless Ceramic Chip Carrier; Q = Cerdip.