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參數資料
| 型號： | AD9801 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor For Electronic Cameras(用于電子照相機的CCD信號處理器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, TQFP-48 |
| 文件頁數： | 8/12頁 |
| 文件大小： | 265K |
| 代理商： | AD9801 |
AD9801
–8–
REV. 0
THEORY OF OPERATION
Introduction
The AD9801 is a 10-bit analog-to-digital interface for CCD
cameras. The block level diagram of the system is shown in
Figure 13. The device includes a correlated double sampler
(CDS), 0 dB–31 dB variable gain amplifier (PGA), black level
correction loop, input clamp and voltage reference. The only
external analog circuitry required at the system level is an emitter
follower buffer between the CCD output and AD9801 inputs.
CLAMP
CDS
BLACK
LEVEL
PGA
10b
ADC
REF
OUT
GAIN
IN
Figure 13.
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a
method for removing several types of noise. Basically, two
samples of the CCD output are taken: one with the signal
present (“data”) and one without (“reference”). Subtracting
these two samples removes any noise that is common—or
correlated—to both.
Figure 14 shows the block diagram of the AD9801’s CDS. The
S/H blocks are directly driven by the input and the sampling
function is performed passively, without the use of amplifiers.
10pF
Q1
S/H
Q2
S/H
S
OUT
FROM
CCD
Figure 14.
This implementation relies on the off-chip emitter follower
buffer to drive the two 10 pF sampling capacitors. Only one
capacitor at a time is seen at the input pin.
The AD9801 actually uses two CDS circuits in a “ping pong”
fashion to allow the system more acquisition time. In this way,
the output from one of the two CDS blocks will be valid for an
entire clock cycle. Thus, the bandwidth requirement of the
subsequent gain stage is reduced as compared to that for a single
CDS channel system. This lower bandwidth translates to lower
power and noise.
Programmable Gain Amplifier (PGA)
The on-chip PGA provides a (linear in dB) gain range of
0 dB–31.5 dB. A typical gain characteristic plot is shown in
Figure 15. Only the range from 0.3 V to 2.7 V is intended for
actual use.
G
PGACONT1 – Volts
Figure 15.
35
–15
0
3
0.5
1
1.5
2
2.5
30
15
0
–5
–10
25
20
10
5
As shown in Figure 16, PGA control is provided through the
PGACONT1 and PGACONT2 inputs. PGACONT1 provides
coarse and PGACONT2 fine (1/16) gain control.
A
PGACONT1
PGACONT2
PGACONT1 = COURSE CONTROL
PGACONT2 = FINE CONTROL (1/16)
Figure 16.
Black Level Clamping
For correct processing, the CCD signal must be referenced to a
well established “black level” by the AD9801. At the edge of the
CCD, there is a collection of pixels that are covered with metal
to prevent any light penetration. As the CCD is read out, these
“black pixels” provide a calibration signal that is used to
establish the black level.
The feedback loop shown in Figure 17 is closed around the
PGA during the calibration interval (CLPOB = LOW) to set the
black level. As the black pixels are being processed, an integrator
block measures the difference between the input level and the
desired reference level. This difference, or error, signal is
amplified and passed to the CDS block where it is added to the
incoming pixel data. As a result of this process, the black pixels
are digitized at one end of the ADC range, taking maximum
advantage of the available linear range of the system.
PGA
ADC
IN
CLPOB
NEG REF
INTEGRATOR
CDS
Figure 17.
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| AD9802 | .50" x 50 Black/Clear 240 Industrial Label Supply RoHS Compliant: NA |
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相關代理商/技術參數 |
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| AD9801JCST | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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| AD9801JST | 制造商:Analog Devices 功能描述: |
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| AD9802JST | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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