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參數(shù)資料
| 型號： | AD9805 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| 中文描述： | 完成12-Bit/10-Bit 6 MSPS的防治荒漠化公約/ CIS信號處理器 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 240K |
| 代理商： | AD9805 |
AD9807/AD9805
–17–
REV. 0
Choosing the Input Coupling Capacitors
Because of the dc offset present at the output of CCDs, it is likely
that these outputs will require some form of dc restoration to be
compatible with the input requirements of the AD9807/AD9805.
T o simplify input level shifting, a dc blocking capacitor may be
used in conjunction with the internal biasing circuits of the
AD9807/AD9805 to accomplish the necessary dc restoration.
Figure 17 shows the equivalent analog input for the VINR,
VING and VINB inputs.
I
BIAS
S1
V
BIAS
AD9807/AD9805
C
V
IN
CDSCLK1
STRTLN
CONFIG
REG 2<7>
CONFIG
REG 2<6>
CONFIG
REG 2<0>
CDSCLK2
CDS
5k
4pF
4pF
Figure 17. Equivalent Analog Inputs (VINR, VING, and
VINB)
Enabling CDS functionality and Line Clamp Mode with Bits 0,
6 and 7 in Configuration Register 2 allows switch S1 to turn on
when ST RT LN is low and CDSCLK 1 goes high. T his connects
a 5 k
biasing resistor to the inputs. T his arrangement acts to
bias the average level of the input signal at voltage, V
BIAS
. T he
voltage, V
BIAS
, changes depending on the selected PGA gain set-
ting. Specifically, for gain settings from 0 to 5, V
BIAS
equals 4 V;
for gain settings from 10 to 15, V
BIAS
equals 3 V. For gain set-
tings between 5 and 10, V
BIAS
decreases linearly from 4 V to 3 V.
T he size of the coupling capacitor is dependent on several
factors including signal swing, allowable droop, and acquisition
time. T he following procedure shows how to determine the
recommended range of capacitors.
Calculating C
MAX
T he maximum capacitor value is largely dependent on the
degree of accuracy and how quickly the input signal must be
level-shifted into the valid input range of the degree of accuracy.
Other factors affecting the speed of the capacitor charging or
Calculating Overall Gain
T he overall gain for the AD9807/AD9805 can accommodate a
wide range of input voltage spans. T he total gain is a composite
of analog gain (from the PGAs), digital gain (from the digital
multiplier) and the input span setting for the A/D (2 V or 4 V). T o
determine the overall gain setting for the AD9807/AD9805, always
multiply the PGA gain setting by the digital gain setting. In
addition, the 2 V/4 V reference option can effectively provide
analog gain for input signals less than 2 V p-p.
Overall Gain
=
Analog Gain
×
Digital Gain
For example, with the PGA gain equal to 1 (gain setting equals
all “zeros”) and the digital multiplier equal to 1, the minimum
gain equals 1. With these settings, input signals can be as large
as 2 V or 4 V depending on the reference setting. Alternatively,
with the PGA gain equal to 4 (gain setting equals all “ones”)
and the digital multiplier equal to 8, the maximum gain equals
32. With the A/D reference span set to 2 V, an input signal span
as small as 62.5 mV p-p will produce a digital output spanning
from all “zeros” to all “ones.” For ranges between 62.5 mV and
4 V, see the Digital Gain and Analog Gain sections of the data
sheet.
Analog Gain
T he transfer function of the PGA is:
Analog Input
=
4
1
+
3
×
15
x
15
where
x
is the decimal representation of the settings in the PGA
gain register. Figure 16 shows the graph of this transfer
function on both a linear and logarithmic scale. T he transfer
function is approximately linear in dB.
12
6
0
10
8
4
2
G
4.0
2.5
1.0
3.5
3.0
2.0
1.5
G
PGA GAIN SETTING
0
13
1
2
3
4
5
6
7
8
9
10 11 12
14 15
GAIN
GAIN (dB)
Figure 16. PGA Transfer Function
Digital Gain
T he digital multiplier section of the AD9807/AD9805 allows the
user to apply gain in addition to that afforded by the analog
PGA. T he minimum gain of the digital multiplier is always 1.
T he user sets the maximum gain of the digital multiplier to be 8,
4, or 2 with Bits 0–2 in the Configuration Register. (T he max
gain is the same for all three channels.) T he digital gain
applied to the output from the digital subtracter is calculated
using the equation:
Digital Gain
=
1
+
Gain
<
n
:0
>
Y
×
X
where
GAIN
<
n
:0> is the decimal representation of the GAIN
bus data bits,
Y
= 4096 for the AD9807, Y = 1024 for the
AD9805, and
X
equals 1, 3 or 7 depending on Bits 0–2 in the
Configuration Register.
Overall T ransfer Function
T he overall transfer function for the AD9807 can be calculated
as follows:
(
2
×
V
REF
ADC
OUT
=
V
IN
±
InputOffset
)
×
PGA Gain
[
]
×
4096
D
OUT
= [
ADC
OUT
+
Offset Register
–
Offset Bus
][
Digital Gain
]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9805JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807 | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9807JS | Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors |
| AD9806 | Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9806KST | Complete 10-Bit 18 MSPS CCD Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9805JS | 制造商:Analog Devices 功能描述:CCD/CIS Signal Processor 64-Pin PQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT ANALOG FRONT END DOC SCANNER - Bulk |
| AD9806 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit 18 MSPS CCD Signal Processor |
| AD9806KST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT 18 MSPS CCD SIGNAL PROCESSOR - Bulk |
| AD9806KSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3.3V 48-Pin LQFP T/R |
| AD9806KSTZ | 功能描述:IC CCD SIGNAL PROC 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
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