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參數資料
| 型號： | AD9814KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Complete 14-Bit CCD/CIS Signal Processor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, SOIC-28 |
| 文件頁數： | 14/15頁 |
| 文件大小： | 160K |
| 代理商： | AD9814KR |
REV. 0
AD9814
–14–
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9814
CDSCLK1
AVDD
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
3
CLOCK INPUTS
8
DATA OUTPUTS
0.1
m
F
3
SERIAL INTERFACE
0.1
m
F
+5V/3V
+5V
0.1
m
F
0.1
m
F
0.1
m
F
0.1
m
F
RED INPUT
GREEN INPUT
BLUE INPUT
0.1
m
F
0.1
m
F
1.0
m
F
10
m
F
0.1
m
F
+
0.1
m
F
+5V
0.1
m
F
Figure 15. Recommended Circuit Configuration, 3-Channel CDS Mode
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9814
CDSCLK1
AVDD
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AVSS
VINR
OFFSET
VING
CML
VINB
CAPT
CAPB
AVSS
AVDD
SLOAD
SCLK
SDATA
3
CLOCK INPUTS
8
DATA OUTPUTS
0.1
m
F
3
SERIAL INTERFACE
0.1
m
F
+5V/3V
+5V
0.1
m
F
RED INPUT
GREEN INPUT
BLUE INPUT
0.1
m
F
10
m
F
0.1
m
F
+
0.1
m
F
+5V
0.1
m
F
Figure 16. Recommended Circuit Configuration, 3-Channel SHA Mode
(Analog Inputs Sampled with Respect to Ground)
APPLICATIONS INFORMATION
Circuit and Layout Recommendations
The recommended circuit configuration for 3-Channel CDS
mode operation is shown in Figure 15. The recommended input
coupling capacitor value is 0.1
μ
F (see Circuit Operation section
for more details). A single ground plane is recommended for the
AD9814. A separate power supply may be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD9814.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC, or by using external
digital buffers. To minimize the effect of digital transients during
major output code transitions, the falling edge of CDSCLK2
should occur coincident with or before the rising edge of
ADCCLK (see Figures 1 through 4 for timing). All 0.1
μ
F
decoupling capacitors should be located as close as possible to
the AD9814 pins. When operating in single channel mode, the
unused analog inputs should be grounded.
Figure 16 shows the recommended circuit configuration for 3-
Channel SHA mode. All of the above considerations also apply
for this configuration, except that the analog input signals are
directly connected to the AD9814 without the use of coupling
capacitors. The analog input signals must already be dc-biased
between 0 V and 4 V (see the Circuit Operation section for
more details).
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| AD9816JS | 制造商:Analog Devices 功能描述:AFE VID 1ADC 12-BIT 5V/5V 44MQFP - Bulk 制造商:Rochester Electronics LLC 功能描述: |
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