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參數(shù)資料
| 型號： | AD9816 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor(12位的采樣速率為6MSPS的CCD/CIS信號處理器) |
| 中文描述： | 完整的12位6 MSPS的防治荒漠化公約/ CIS信號處理器（12位的采樣速率為6MSPS的防治荒漠化公約/獨聯(lián)體信號處理器） |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 190K |
| 代理商： | AD9816 |
AD9816
–14–
REV. A
APPLICATIONS INFORMATION
CDS Mode Circuit
The recommended circuit configuration for CDS mode opera-
tion is shown in Figure 20. The input coupling capacitor value
of 1200 pF is recommended, but this value may be adjusted to
suit a particular application (see Circuit Descriptions). A single
ground plane is recommended for the AD9816. A separate power
supply may be used for DRVDD, the digital driver supply, but this
AVDD
AVSS
CAPT
CAPT
CAPB
CAPB
VREF
CML
VINR
AVSS
VING
A
V
A
A
O
C
C
A
D
D
N
DRVSS
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
DVSS
SLOAD
SDATA
SCLK
P
P
N
O
D
D
D
D
D
D
D
AD9816
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
4
4
4
4
4
3
3
3
3
3
3
1
1
1
1
1
1
1
1
2
2
2
O
D
D
D
D
D
D
0.01
m
F
0.1
m
F
V
DD
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
SLOAD
SDATA
SCLK
0.01
m
F
0.1
m
F
V
DD
1200pF
1200pF
1200pF
RED_IN
GREEN_IN
BLUE_IN
1.0
m
F
+
0.1
m
F
10
m
F
+
10
m
F
0.1
m
F
0.1
m
F
0.1
m
F
0.01
m
F
0.1
m
F
V
DD
V
DD
0.1
m
F
0.01
m
F
ADCCLK
CDSCLK2
CDSCLK1
V
DD
1k
V
0.1
m
F
1.0
m
F
1.5k
V
NC = NO CONNECT
Figure 20. Recommended Circuit for CDS Mode
supply pin should still be decoupled to the same ground plane
as the rest of the AD9816. The loading of the digital outputs
should be minimized, either by using short traces to the digital
ASIC, or by using external digital buffers. All 0.01
μ
F and
0.1
μ
F decoupling capacitors should be located as close as pos-
sible to the AD9816 pins. Also, the 1200 pF input capacitors
should be located close the AD9816’s analog input pins.
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