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參數資料
| 型號： | AD9821KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 1.40 MM, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數： | 11/16頁 |
| 文件大小： | 277K |
| 代理商： | AD9821KST |
REV. 0
AD9821
–11–
CIRCUIT DESCRIPTION AND OPERATION
The AD9821 signal processing chain is shown in Figure 10.
Each processing step is essential in achieving a high quality
image from the raw imager pixel data.
Differential Input SHA
The differential input SHA circuit is designed to accommodate
a variety of different image sensor output voltages. The timing
shown in Figure 8 illustrates how the DATACLK signal is used to
sample both the VIN+ and VIN– signals simultaneously. The
imager signal is sampled on the rising edges of DATACLK.
Placement of this clock signal is critical in achieving the best
performance from the imager. An internal DATACLK delay (t
ID
)
of 3 ns is caused by internal propagation delays.
The differential input can be used in a variety of single-ended
and differential configurations, as shown in Table VI. The
allowable voltage range for both VIN+ or VIN– is from 0 V
to 1.8 V. Signal levels outside this range will result in severely
degraded performance. Regardless of the input configuration,
the voltage sampled by the SHA is always equal to VIN+ minus
VIN–. VIN+ must always be equal to or greater than VIN– or
0dB TO 36dB
BYP1
VIN+
DIGITAL
FILTERING
CLPOB
OPTICAL BLACK
CLAMP
DOUT
12-BIT
ADC
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
10
SHA
INTERNAL
VREF
12
REFT
REFB
1.0V
2.0V
DATACLK
VIN–
0.45V
INTERNAL
BIAS
PBLK
0.1 F
1.0 F
1.0 F
Figure 10. Internal Block Diagram
negative clipping will occur. A small amount of offset between
the VIN+ and VIN– signals is allowable and can be corrected by
the Optical Black Clamp, up to
±
30 mV.
Note that the VIN+ and VIN– inputs do not contain any dc
restoration or bias circuitry. Therefore, dc-coupling is recom-
mended when driving the AD9821 analog inputs. If ac-coupling is
used, external biasing circuitry must be provided for the VIN+
and VIN– inputs to keep them in the acceptable common-mode
voltage range of 0 V to 1.8 V.
Table VI. Example Input Voltage Configurations
VIN+ Range (V) VIN– Range (V) SHA Output Range (V)
Black White
Black
White
Black
White
0
0.5
1.0
0.5
1.0
1.0
1.5
1.5
1.0
1.0
0
0.5
1.0
0.5
1.0
0
0.5
0.5
0
0
0
0
0
0
0
1.0
1.0
1.0
1.0
1.0
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相關代理商/技術參數 |
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| AD9821KSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 40 MSPS IMAGING SIGNAL PROCESSOR - Tape and Reel |
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| AD9821KSTZRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R |
| AD9821KSTZRL7 | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9822 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 14-Bit CCD/CIS Signal Processor |
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