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參數資料
| 型號： | AD9826KRS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Complete 16-Bit Imaging Signal Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | 5.30 MM, SSOP-28 |
| 文件頁數： | 15/20頁 |
| 文件大小： | 159K |
| 代理商： | AD9826KRS |
AD9826
–15–
REV. A
MUX Configuration Register
T he MUX Configuration Register controls the sampling chan-
nel order and the 2-Channel Mode configuration in the AD9826.
Bits D8 and D3–D0 should always be set low. Bit D7 is used
when operating in 3-Channel or 2-Channel Mode. Setting Bit
D7 high will sequence the MUX to sample the Red channel
first, then the Green channel, and then the Blue channel. When
in 3-channel mode, the CDSCLK2 pulse always resets the MUX
to sample the Red channel first (see Figure 11). When Bit D7 is
set low, the channel order is reversed to Blue first, Green sec-
ond, and Red third. T he CDSCLK 2 pulse will always reset the
MUX to sample the Blue channel first. Bits D6, D5, and D4 are
used when operating in 1 or 2-Channel Mode. Bit D6 is set high
to sample the Red channel. Bit D5 is set high to sample the
Green channel. Bit D4 is set high to sample the Blue channel.
T he MUX will remain stationary during 1-channel mode. T wo-
Channel Mode is selected by setting two of the channel select
Bits (D4–D6) high. T he MUX samples the channels in the
order selected by Bit D7.
PGA Gain Registers
T here are three PGA registers for individually programming the
gain in the Red, Green, and Blue channels. Bits D8, D7, and
D6 in each register must be set low, and Bits D5 through D0
control the gain range from 1
×
to 6
×
in 64 increments. See
Figure 17 for a graph of the PGA gain versus PGA register
code. T he coding for the PGA registers is straight binary, with
an all “zeros” word corresponding to the minimum gain setting
(1
×
) and an all “ones” word corresponding to the maximum
gain setting (6
×
).
Offset Registers
T here are three Offset Registers for individually programming
the offset in the Red, Green, and Blue channels. Bits D8 through
D0 control the offset range from –300 mV to +300 mV in 512
increments. T he coding for the Offset Registers is Sign Mag-
nitude, with D8 as the sign bit. T able V shows the offset range
as a function of the Bits D8 through D0.
T able III. MUX Configuration Register Settings
D
8
D7
D6
D5
D4
D3
D2
D1
D0
Set
to
0
MUX Order
Channel Select
Channel Select
Channel Select
Set
to
0
Set
to
0
Set
to
0
Set
to
0
1 = R-G-B
*
0 = B-G-R
1 = RED
*
0 = Off
1 = GREEN
0 = Off
*
1 = BLUE
0 = Off
*
*
Power-on default value.
T able IV. PGA Gain Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Gain (V/V)
Gain (dB)
Set to 0
0
0
Set to 0
0
0
Set to 0
0
0
MSB
0
0
LSB
0
*
1
0
0
1
1
0
0
0
0
0
0
1.0
1.013
5.56
6.0
0.0
0.12
14.9
15.56
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
*
Power-on default value.
T able V. Offset Register Settings
D8
D7
D6
D5
D4
D3
D2
D1
D0
Offset (mV)
MSB
0
0
LSB
0
*
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
+1.2
+300
0
–1.2
–300
0
1
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
*
Power-on default value.
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相關代理商/技術參數 |
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| AD9826KRSRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 16-Bit 5V 28-Pin SSOP T/R |
| AD9826KRSZ | 功能描述:IC IMAGE SGNL PROC 16BIT 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9826KRSZRL | 功能描述:IC IMAGE SGNL PROC 16BIT 28-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9828JST | 制造商:Analog Devices 功能描述: |
| AD9828JSTRL | 制造商:Analog Devices 功能描述: |
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